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參數(shù)資料
| 型號： | DC951A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 22/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2481 |
| 軟件下載： | QuikEval System |
| 設計資源： | DC951A Design File DC951A Schematic |
| 標準包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2481 |
| 已供物品： | 板 |
| 相關產品： | LTC2481HDD#TRPBF-ND - IC ADC DELTA SIGMA 16BIT 10DFN LTC2481HDD#PBF-ND - IC ADC 16BIT I2C 7.5SPS 10DFN LTC2481CDD#TRPBF-ND - IC ADC 16BIT I2C 10-DFN LTC2481IDD#TRPBF-ND - IC ADC 16BIT I2C 10-DFN LTC2481IDD#PBF-ND - IC ADC 16BIT I2C 10-DFN LTC2481CDD#PBF-ND - IC ADC 16BIT I2C 10-DFN |
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LTC2481
29
2481fc
APPLICATIONS INFORMATION
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is
a high gain, low bandwidth amplier stage followed by a
high bandwidth unity-gain buffer.
When external ampliers are driving the LTC2481, the
ADC input referred system noise calculation can be
simplied by Figure 30. The noise of an amplier driving
the LTC2481 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass lter with a
corner frequency fi. The amplier noise spectral density
is ni. From Figure 30, using fi as the x-axis selector, we
can nd on the y-axis the noise equivalent bandwidth freqi
of the input driving amplier. This bandwidth includes
the band limiting effects of the ADC internal calibration
and ltering. The noise of the driving amplier referred
to the converter input and including all these effects can
be calculated as N = ni √freqi. The total system noise
(referred to the LTC2481 input) can now be obtained by
summing as square root of sum of squares the three
ADC input referred noise sources: the LTC2481 internal
noise, the noise of the IN+ driving amplier and the noise
of the IN– driving amplier.
If the CA0/f0 pin is driven by an external oscillator of
frequency fEOSC, Figure 30 can still be used for noise
calculation if the x-axis is scaled by fEOSC/307200.
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS10fS11fS12fS
INPUT
NORMAL
MODE
REJECTION
(dB)
2481 F31
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
For large values of the ratio fEOSC/307200, the Figure 30
plot accuracy begins to decrease, but at the same time
the LTC2481 noise oor rises and the noise contribution
of the driving ampliers lose signicance.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital ltering. Combined
with a large oversampling ratio, the LTC2481 signicantly
simplies antialiasing lter requirements. Additionally,
the input current cancellation feature of the LTC2481
allows external lowpass ltering without degrading the
DC performance of the device.
The SINC4 digital lter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2481’s autocalibration circuits further simplify the
antialiasing requirements by additional normal mode
signal ltering both in the analog and digital domain.
Independent of the operating mode, fS = 256 fN = 2048
fOUTMAX where fN is the notch frequency and fOUTMAX
is the maximum output data rate. In the internal oscilla-
tor mode with a 50Hz notch setting, fS = 12800Hz, with
50Hz/60Hz rejection, fS = 13960Hz and with a 60Hz notch
setting fS = 15360Hz. In the external oscillator mode, fS =
fEOSC/20. The performance of the normal mode rejection
is shown in Figures 31 and 32.
Figure 31. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch Mode
Figure 32. Input Normal Mode Rejection at DC
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0fS
INPUT
NORMAL
MODE
REJECTION
(dB)
2481 F32
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
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