參數(shù)資料
型號： DC798B
廠商： Linear Technology
文件頁數(shù)： 17/42頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2480
軟件下載： QuikEval System
設(shè)計資源： DC798B Design File
DC798B Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
已用 IC / 零件： LTC2480
已供物品： 板
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LTC2480
2480fd
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
theconversionresultandaCSsignaltomonitorandcontrol
the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resis-
tor is active on the SCK pin during the falling edge of CS;
therefore,theinternalserialclocktimingmodeisautomati-
cally selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC
= 0), the device will exit the low power mode during the
EOC test. In order to allow the device to return to the low
power sleep state, CS must be pulled HIGH before the first
rising edge of SCK. In the internal SCK timing mode, SCK
goes HIGH and the device begins outputting data at time
tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest
after EOC goes LOW (if CS is LOW during the falling edge
of EOC). The value of tEOCtest is 12s if the device is using
its internal oscillator. If fO is driven by an external oscillator
of frequency fEOSC, then tEOCtest is 3.6/fEOSC in seconds. If
CS is pulled HIGH before time tEOCtest, the device returns
to the sleep state and the conversion result is held in the
internal static shift register.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 24th rising edge. The input data is shifted in via
the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result on the 24th rising edge of
SCK.Afterthe24thrisingedge,SDOgoesHIGH(EOC = 1),
SCK stays HIGH and a new conversion starts.
applicaTions inForMaTion
EN
GS2
GS1
GS0
IM
FA
FB
SPD
SDI*
DON’T CARE
SDO
SCK
(INTERNAL)
CS
MSB
SIG
BIT 0
LSB
IM
BIT 4
TEST EOC
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
EOC
BIT 23
SLEEP
DATA OUTPUT
CONVERSION
2480 F08
<tEOCtest
Hi-Z
TEST EOC
VCC
FO
VREF
IN+
IN–
SCK
SDI
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
10k
VCC
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUT
1F
2.7V TO 5.5V
LTC2480
4-WIRE
SPI INTERFACE
Figure 8. Internal Serial Clock, Single Cycle Operation
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