Frequency Rejection Selection (FO) The LTC2412 internal oscilla" />
參數(shù)資料
型號(hào)： DC746A
廠商： Linear Technology
文件頁(yè)數(shù)： 7/36頁(yè)
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2412
軟件下載： QuikEval System
設(shè)計(jì)資源： DC746A Design File
DC746A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2412
已供物品： 板
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LTC2412
15
2412f
Frequency Rejection Selection (FO)
The LTC2412 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics for 50Hz
±2% or 60Hz ±2%. For 60Hz rejec-
tion, FO should be connected to GND while for 50Hz
rejection the FO pin should be connected to VCC.
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2412 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The exter-
nal clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods tHEO and tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2412 provides better than 110dB
normal mode rejection in a frequency range fEOSC/2560
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/2560
is shown in Figure 4.
Whenever an external clock is not present at the FO pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2412
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
Figure 4. LTC2412 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
APPLICATIO S I FOR ATIO
WU
U
Table 2. LTC2412 Output Data Format
Differential Input Voltage
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
…
Bit 0
VIN*
EOC
CH0/CH1
SIG
MSB
VIN* ≥ 0.5 VREF**
0
0/1
1
0
…
0
0.5 VREF** – 1LSB
0
0/1
1
0
1
…
1
0.25 VREF**
0
0/1
1
0
1
0
…
0
0.25 VREF** – 1LSB
0
0/1
1
0
1
…
1
0
0/1
1
0
…
0
–1LSB
0
0/1
0
1
…
1
– 0.25 VREF**
0
0/1
0
1
0
…
0
– 0.25 VREF** – 1LSB
0
0/1
0
1
0
1
…
1
– 0.5 VREF**
0
0/1
0
1
0
…
0
VIN* < –0.5 VREF**
0
0/1
0
1
…
1
*The differential input voltage VIN = IN+ – IN–.
**The differential reference voltage VREF = REF+ – REF–.
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)
–12
–8
–4
0
4
8
12
NORMAL
MODE
REJECTION
(dB)
2412 F04
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
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