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參數(shù)資料
| 型號： | DC245A-A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL LTC1668 |
| 設(shè)計資源： | DC245A Design File DC245A Schematic |
| 標準包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 50M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時間： | 20ns |
| DAC 型： | 電流 |
| 工作溫度： | 0°C ~ 70°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTC1668 |
| 相關(guān)產(chǎn)品： | LTC1668CG#PBF-ND - IC DAC 16BIT 50MSPS 28-SSOP LTC1668IG#PBF-ND - IC D/A CONV 16BIT 50MSPS 28-SSOP LTC1668CG#TRPBF-ND - IC D/A CONV 16BIT 50MSPS 28-SSOP LTC1668IG#TRPBF-ND - IC D/A CONV 16BIT 50MSPS 28-SSOP LTC1668IG-ND - IC DAC 16BIT 50MSPS 28SSOP LTC1668IG#TR-ND - IC DAC 16BIT 50MSPS 28SSOP LTC1668CG#TR-ND - IC DAC 16BIT 50MSPS 28SSOP LTC1668CG-ND - IC D/A CONV 16BIT 50MSPS 28-SSOP |
13
LTC1666/LTC1667/LTC1668
APPLICATIO S I FOR ATIO
WU
UU
LADCOM
The LADCOM pin is the common connection for the
internal DAC attenuator ladder. It usually is tied to analog
ground, but more generally it should connect to the same
potential as the load resistors on IOUT A and IOUT B. The
LADCOM pin carries a constant current to VSS of approxi-
mately 0.32 (IOUTFS), plus any current that flows from
IOUT A and IOUT B through the RIOUT A and RIOUT B resistors.
Output Compliance
The specified output compliance voltage range is
±1V. The
DC linearity specifications, INL and DNL, are trimmed and
guaranteed on IOUT A into the virtual ground of an
I-to-V converter, but are typically very good over the full
output compliance range. Above 1V the output current will
start to increase as the DAC current steering switch
impedance decreases, degrading both DC and AC linear-
ity. Below –1V, the DAC switches will start to approach the
transition from saturation to linear region. This will de-
grade AC performance first, due to nonlinear capacitance
and increased glitch impulse. AC distortion performance
is optimal at amplitudes less than
±0.5VP-P on IOUT A and
IOUT B due to nonlinear capacitance and other large-signal
effects. At first glance, it may seem counter-intuitive to
decrease the signal amplitude when trying to optimize
SFDR. However, the error sources that affect AC perfor-
mance generally behave as additive currents, so decreas-
ing the load impedance to reduce signal voltage amplitude
will reduce most spurious signals by the same amount.
Figure 4. AC Characterization Setup (LTC1668)
–
+
16-BIT
HIGH SPEED
DAC
HP1663EA
LOGIC ANALYZER WITH
PATTERN GENERATOR
VSS
VDD
–5V
LADCOM
AGND DGND
CLK
DB15
DB0
16
DIGITAL
DATA
CLK
IN
1666/7/8 F05
IOUT A
0.1
F
LTC1668
5V
IREFIN
REFOUT
COMP1
COMP2
C2
0.1
F
0.1
F
OUT 1 OUT 2
C1
0.1
F
RSET
2k
IOUT B
HP8110A DUAL
PULSE GENERATOR
LOW JITTER
CLOCK SOURCE
CLK
IN
50
0.1
F
50
TO HP3589A
SPECTRUM
ANALYZER
50
INPUT
110
MINI-CIRCUITS
T1–1T
2.5V
REFERENCE
Figure 3. Equivalent Analog Output Circuit
20
19
23
18
RIOUT B
1.1k
5pF
–5V
1666/7/8 F04
RIOUT A
1.1k
LADCOM
IOUT A
IOUT B
VSS
52.3
52.3
LTC1666/LTC1667/LTC1668
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