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參數(shù)資料
| 型號： | DC1783A-G |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 23/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2377-18 |
| 軟件下載： | QuikEval II System |
| 設(shè)計資源： | DC1783A Design Files DC1783A Schematic |
| 標準包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標準）： | 6.8mW @ 500kSPS |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2377-18 |
| 已供物品： | 板 |
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LTC2377-18
8
237718f
CHAIN (Pin 1): Chain Mode Selector Pin. When low, the
LTC2377-18 operates in normal mode and the RDL/SDI
input pin functions to enable or disable SDO. When high,
the LTC2377-18 operates in chain mode and the RDL/SDI
pin functions as SDI, the daisy-chain serial data input.
Logic levels are determined by 0VDD.
VDD (Pin 2): 2.5V Power Supply. The range of VDD is
2.375V to 2.625V. Bypass VDD to GND with a 10μF ceramic
capacitor.
GND (Pins 3, 6, 10 and 16): Ground.
IN+, IN– (Pins 4, 5):
Positive and Negative Differential
Analog Inputs.
REF (Pin 7): Reference Input. The range of REF is 2.5V
to 5.1V. This pin is referred to the GND pin and should be
decoupled closely to the pin with a 47μF ceramic capacitor
(X5R, 0805 size).
REF/DGC (Pin 8): When tied to REF, digital gain compression
is disabled and the LTC2377-18 defines full-scale according
to the ±VREF analog input range. When tied to GND, digital
gain compression is enabled and the LTC2377-18 defines
full-scale with inputs that swing between 10% and 90%
of the ±VREF analog input range.
CNV (Pin 9): Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by 0VDD.
BUSY (Pin 11): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by 0VDD.
RDL/SDI (Pin 12): When CHAIN is low, the part is in nor-
mal mode and the pin is treated as a bus enabling input.
When CHAIN is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisy chain is input. Logic levels are
determined by 0VDD.
SCK (Pin 13): Serial Data Clock Input. When SDO is enabled,
the conversion result or daisy-chain data from another
ADC is shifted out on the rising edges of this clock MSB
first. Logic levels are determined by 0VDD.
SDO (Pin 14): Serial Data Output. The conversion result or
daisy-chain data is output on this pin on each rising edge
of SCK MSB first. The output data is in 2’s complement
format. Logic levels are determined by 0VDD.
OVDD (Pin 15): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1μF capacitor.
GND (Exposed Pad Pin 17 – DFN Package Only): Ground.
Exposed pad must be soldered directly to the ground plane.
FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTIONS
REF = 5V
LTC2377-18
IN+
VDD = 2.5V
OVDD = 1.8V to 5V
IN–
CHAIN
CNV
GND
BUSY
REF/DGC
SDO
SCK
RDL/SDI
CONTROL LOGIC
18-BIT SAMPLING ADC
SPI
PORT
+
–
237718 BD01
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