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參數(shù)資料
| 型號： | DC1444A-B |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD SAR ADC LTC2305 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC1444A Design File DC1444A Schematic |
| 標準包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 14k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 在以下條件下的電源（標準）： | 1.5mW @ 1kSPS |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2305 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2305IMS#TRPBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305IDE#TRPBF-ND - IC ADC 12-BIT 2CHN 12-DFN LTC2305IDE#PBF-ND - IC ADC 12-BIT 2CHN 12-DFN LTC2305HMS#TRPBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305HMS#PBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305CMS#TRPBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305CMS#PBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305CDE#TRPBF-ND - IC ADC 12-BIT 2CHN 12-DFN LTC2305CDE#PBF-ND - IC ADC 12-BIT 2CHN 12-DFN LTC2305IMS#PBF-ND - IC ADC 12BIT I2C 12-MSOP |
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LTC2301/LTC2305
19
23015fb
APPLICATIONS INFORMATION
Continuous Read/Write
Once the conversion cycle is complete, the LTC2301/
LTC2305 can be written to and then read from using the
repeated START (Sr) command. Figure 9 shows a cycle
which begins with a data write, a repeated START, followed
by a read and concluded with a STOP command. After
all 16 bits are read out, a conversion may be initiated by
issuing a STOP command. The following conversion will
be performed using the newly programmed data.
Synchronizing Multiple LTC2301/LTC2305s with a
Global Address Call
In applications where several LTC2301/LTC2305s or other
I2C SAR ADCs from Linear Technology Corporation are
used on the same I2C bus, all converters can be synchro-
nized through the use of a global address call. Prior to
issuing the global address call, all converters must have
completed a conversion cycle. The master then issues a
START, followed by the global address 1101011, and a
write request. All converters will be selected and acknowl-
edge the request. The master then sends a write byte
(optional) followed by the STOP command. This will update
the channel selection (optional) and simultaneously initi-
ate a conversion for all ADCs on the bus (see Figure 10).
In order to synchronize multiple converters without chang-
ing the channel, a STOP command may be issued after
acknowledgement of the global write command. Global
read commands are not allowed and the converters will
NACK a global read request.
Nap Mode
The ADCs enter nap mode after a conversion is complete
(tCONV) if the SLP bit is set to a logic 0. The supply current
decreases to 225μA in nap mode between conversions,
thereby reducing the average power dissipation as the
sample rate decreases. For example, the LTC2301/LTC2305
draw an average of 300μA at a 1ksps sampling rate. The
LTC2301/LTC2305 keep only the reference (VREF) and
reference buffer (REFCOMP) circuitry active when in nap
mode.
Figure 9. Write, Read, START Conversion
Figure 10. Synchronize Multiple LTC2301/LTC2305s with a Global Address Call
S
CONVERSION
NAP
DATA INPUT
ADDRESS
CONVERSION
DATA
OUTPUT
W
ACK
WRITE
7-BIT ADDRESS
Sr
R
ACK
23015 F09
READ
7-BIT ADDRESS
P
S
SDA
SCL
CONVERSION
NAP
LTC2301/LTC2305
DATA OUTPUT
CONVERSION OF ALL LTC2301/05s
W
ACK
WRITE (OPTIONAL)
GLOBAL ADDRESS
P
LTC2301/LTC2305
23015 F10
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