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參數(shù)資料
| 型號(hào)： | DC1112A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DAC LTC2755-16 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC1112A Design File DC1112A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™, SoftSpan™ |
| DAC 的數(shù)量： | 4 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時(shí)間： | 2µs |
| DAC 型： | 電流 |
| 工作溫度： | 0°C ~ 70°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTC2755-16 |
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LTC2755
6
2755f
CODE
0
–1.0
INL
(LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
16384
32768
–0.6
0.6
0.8
0.2
49152
65535
2755 G01
VDD = 5V
VREF = 5V
±10V RANGE
CODE
0
–1.0
DNL
(LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
16384
32768
–0.6
0.6
0.8
0.2
49152
65535
2755 G02
VDD = 5V
VREF = 5V
±10V RANGE
TEMPERATURE (°C)
–40
–1.0
INL
(LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
–20
20
0
40
–0.6
0.6
0.8
0.2
60
80
2755 G04
VDD = 5V
VREF = 5V
±10V RANGE
+INL
–INL
INL vs Temperature
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
LTC2755-16
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD = 2.7V to 3.3V
t22
READ Falling Edge to UPD Rising Edge
(Note 11)
●
10
ns
t23
I/O Bus Hi-Z to Read Rising Edge
(Note 11)
●
0ns
t24
Read Falling Edge to I/O Bus Active
(Note 11)
●
35
ns
CLR Timing
t25
CLR Pulse Width Low
●
20
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specied maximum operating
junction temperature may impair device reliability.
Note 3: Because of the proprietary SoftSpan switching architecture, the
measured resistance looking into each of the specied pins is constant for
all output ranges if the IOUT1X and IOUT2X pins are held at ground.
Note 4: R1 measured from RIN1 to RCOM1; R2 measured from REFA to
RCOM1; R3 measured from RIN2 to RCOM2; R4 measured from REFC to
RCOM2.
Note 5: Using LT1469 with CFEEDBACK = 15pF. A ±0.0015% settling time
of 1.7μs can be achieved by optimizing the time constant on an individual
basis. See Application Note 74, Component and Measurement Advances
Ensure 16-Bit DAC Settling Time.
Note 6: Measured at the major carry transition, 0V to 5V range. Output
amplier: LT1469; CFB = 27pF.
Note 7. Full-scale transition; REF = 0V.
Note 8. Analog Crosstalk is dened as the AC voltage ratio VOUTB/VREFA,
expressed in dB. REFB is grounded, and DAC B is set to 0V-5V span and
zero-, mid- or full- scale code. VREFA is a 3VRMS, 1kHz sine wave. Crosstalk
between other DAC channels is similar or better.
Note 9. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplier = LT1469.
Note 10. Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B =
bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full- scale.
Note 11. Guaranteed by design, not subject to test.
TIMING CHARACTERISTICS The ● denotes specications that apply over the full operating temperature range,
otherwise specications are at TA = 25°C.
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
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