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參數(shù)資料
| 型號： | DC1011A-A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 17/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2498 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC1011A Schematic DC1011A Design Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2498 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2498HUHF#TRPBF-ND - IC ADC 24BIT 16CH DELTA 38-QFN LTC2498HUHF#PBF-ND - IC ADC 24BIT 16CH DELTA 38-QFN LTC2498IUHF#TRPBF-ND - IC ADC 24BIT 16CH 38-QFN LTC2498CUHF#TRPBF-ND - IC ADC 24BIT 16CH 38-QFN LTC2498IUHF#PBF-ND - IC ADC 24BIT 16CH 38-QFN LTC2498CUHF#PBF-ND - IC ADC 24BIT 16CH 38-QFN |
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LTC2498
24
2498ff
applications inForMation
Figure 8. External Serial Clock, 3-Wire Operation (CS = 0)
progress and EOC = 0 once the conversion is complete.
On the falling edge of EOC, the conversion result is load-
ing into an internal static shift register. The output data
can now be shifted out the SDO pin under control of the
externally applied SCK signal. Data is updated on the fall-
ing edge of SCK. The input data is shifted into the device
through the SDI pin on the rising edge of SCK. On the
32nd falling edge of SCK, SDO goes HIGH, indicating a
new conversion has begun. This data now serves as EOC
for the next conversion.
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle, see Figure 9.
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating or pulled HIGH
before the conclusion of the POR cycle and prior to each
fallingedgeofCS.Aninternalweakpull-upresistorisactive
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may
be pulled LOW in order to monitor the state of the con-
verter. Once CS is pulled LOW, SCK goes LOW and EOC
is output to the SDO pin. EOC = 1 while the conversion is
in progress and EOC = 0 if the device is in the sleep state
When testing EOC, if the conversion is complete (EOC =
0), the device will exit sleep state. In order to return to the
sleepstateandreducethepowerconsumption,CSmustbe
pulled HIGH before the device pulls SCK HIGH. When the
device is using its own internal oscillator (fO is tied LOW),
the first rising edge of SCK occurs 12s (tEOCTEST = 12s)
after the falling edge of CS. If fO is driven by an external
oscillator of frequency fEOSC, then tEOCTEST = 3.6/fEOSC.
If CS remains LOW longer than tEOCTEST, the first rising
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
After the 32nd rising edge of SCK a new conversion au-
tomatically begins. SDO goes HIGH (EOC = 1) and SCK
VCC
fO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28
35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2498
3-WIRE
SPI INTERFACE
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2498 F08
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
BIT 29
BIT 30
BIT 31
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
ODD
BIT 18 BIT 17
BIT 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
DON'T CARE
MSB
SIG
“0”
10F
0.1F
2.7V TO 5.5V
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