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參數(shù)資料
型號： DC1010A-A
廠商： Linear Technology
文件頁數(shù)： 27/32頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2493
軟件下載： QuikEval System
設(shè)計資源： DC1010A Design File
DC1010A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： Easy Drive™, QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 15
數(shù)據(jù)接口： I²C，串行
已用 IC / 零件： LTC2493
已供物品： 板
相關(guān)產(chǎn)品： LTC2493IDE#TRPBF-ND - IC ADC 24BIT DELTA SIG 14-DFN
LTC2493CDE#TRPBF-ND - IC ADC 24BIT DELTA SIG 14-DFN
LTC2493CDE#PBF-ND - IC ADC 24BIT DELTA SIG 14-DFN
LTC2493IDE#PBF-ND - IC ADC 24BIT DELTA SIG 14-DFN
LTC2493
4
2493fd
i2c inpuTs anD DigiTal ouTpuTs The
l
denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
analog inpuT anD reFerence The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IN+
Absolute/Common Mode IN+ Voltage
(IN+ Corresponds to the Selected Positive Input Channel)
GND – 0.3V
VCC + 0.3V
V
IN–
Absolute/Common Mode IN– Voltage
(IN– Corresponds to the Selected Negative Input Channel)
GND – 0.3V
VCC + 0.3V
V
VIN
Input Differential Voltage Range (IN+ – IN–)
l
–FS
+FS
V
FS
Full-Scale of the Differential Input (IN+ – IN–)
l
0.5VREF
V
LSB
Least Significant Bit of the Output Code
l
FS/224
REF+
Absolute/Common Mode REF+ Voltage
l
0.1
VCC
V
REF–
Absolute/Common Mode REF– Voltage
l
GND
REF+ – 0.1V
V
VREF
Reference Voltage Range (REF+ – REF–)
l
0.1
VCC
V
CS(IN+)
IN+ Sampling Capacitance
11
pF
CS(IN–)
IN– Sampling Capacitance
11
pF
CS(VREF)
VREF Sampling Capacitance
11
pF
IDC_LEAK(IN+)
IN+ DC Leakage Current
Sleep Mode, IN+ = GND
l
–10
1
10
nA
IDC_LEAK(IN–)
IN– DC Leakage Current
Sleep Mode, IN– = GND
l
–10
1
10
nA
IDC_LEAK(REF+) REF+ DC Leakage Current
Sleep Mode, REF+ = VCC
l
–100
1
100
nA
IDC_LEAK(REF–) REF– DC Leakage Current
Sleep Mode, REF– = GND
l
–100
1
100
nA
tOPEN
MUX Break-Before-Make
50
ns
QIRR
MUX Off Isolation
VIN = 2VP-P DC to 1.8MHz
120
dB
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
High Level Input Voltage
l
0.7VCC
V
VIL
Low Level Input Voltage
l
0.3VCC
V
VIHA
Low Level Input Voltage for Address Pins CA0, CA1 and
Pin fO
l
0.05VCC
V
VILA
High Level Input Voltage for Address Pins CA0, CA1
l
0.95VCC
V
RINH
Resistance from CA0, CA1 to VCC to Set Chip Address
Bit to 1
l
10
kΩ
RINL
Resistance from CA0, CA1 to GND to Set Chip Address
Bit to 0
l
10
kΩ
RINF
Resistance from CA0, CA1 to GND or VCC to Set Chip
Address Bit to Float
l
2
MΩ
II
Digital Input Current (fO)
l
–10
10
A
VHYS
Hysteresis of Schmitt Trigger Inputs
(Note 5)
l
0.05VCC
V
VOL
Low Level Output Voltage (SDA)
I = 3mA
l
0.4
V
tOF
Output Fall Time VIH(MIN) to VIL(MAX)
Bus Load CB 10pF to
400pF (Note 14)
l
20 + 0.1CB
250
ns
IIN
Input Leakage (SDA, SCL)
0.1VCC ≤ VIN ≤ 0.9VCC
l
1
A
CCAX
External Capacitative Load On-Chip Address Pins (CA0,
CA1) for Valid Float
l
10
pF
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