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參數(shù)資料
| 型號： | DAC8831IRGYTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 1 us SETTLING TIME, 16-BIT DAC, PQCC14 |
| 封裝： | GREEN, PLASTIC, QFN-14 |
| 文件頁數(shù)： | 27/29頁 |
| 文件大小： | 687K |
| 代理商： | DAC8831IRGYTG4 |
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TIMING CHARACTERISTICS: VDD = +5 V
(1) (2)
TIMING CHARACTERISTICS: VDD = +3 V
(1) (2)
SLAS449D – FEBRUARY 2005 – REVISED SEPTEMBER 2007
At –40
°C to +85°C, unless otherwise noted.
PARAMETER
MIN
MAX
UNIT
tsck
SCLK period
20
ns
twsck
SCLK high or low time
10
ns
tDelay
Delay from SCLK high to CS low
10
ns
tLead
CS enable lead time
10
ns
tLag
CS enable lag time
10
ns
tDSCLK
Delay from CS high to SCLK high
10
ns
ttd
CS high between active period
30
ns
tsu
Data setup time (input)
10
ns
tho
Data hold time (input)
0
ns
tWLDAC
LDAC width
30
ns
tDLDAC
Delay from CS high to LDAC low
30
ns
VDD high to CS low (power-up delay)
10
μs
(1)
Assured by design. Not production tested.
(2)
Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
At –40
°C to +85°C, unless otherwise noted.
PARAMETER
MIN
MAX
UNIT
tsck
SCLK period
20
ns
twsck
SCLK high or low time
10
ns
tDelay
Delay from SCLK high to CS low
10
ns
tLead
CS enable lead time
10
ns
tLag
CS enable lag time
10
ns
tDSCLK
Delay from CS high to SCLK high
10
ns
ttd
CS high between active period
30
ns
tsu
Data setup time (input)
10
ns
tho
Data hold time (input)
0
ns
tWLDAC
LDAC width
30
ns
tDLDAC
Delay from CS high to LDAC low
30
ns
VDD high to CS low (power-up delay)
10
μs
(1)
Assured by design. Not production tested.
(2)
Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
Copyright 2005–2007, Texas Instruments Incorporated
7
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