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參數(shù)資料
| 型號： | DAC8531E/2K5G4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO8 |
| 封裝： | GREEN, PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 21/26頁 |
| 文件大小： | 749K |
| 代理商： | DAC8531E/2K5G4 |
DAC8531
4
SBAS192B
www.ti.com
SERIAL WRITE OPERATION
SCLK
SYNC
D
IN
DB23
DB0
t
8
t
3
t
2
t
7
t
4
t
5
t
6
t
1
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNITS
t1(3)
SCLK Cycle Time
VDD = 2.7V to 3.6V
50
ns
VDD = 3.6V to 5.5V
33
ns
t2
SCLK HIGH Time
VDD = 2.7V to 3.6V
13
ns
VDD = 3.6V to 5.5V
13
ns
t3
SCLK LOW Time
VDD = 2.7V to 3.6V
22.5
ns
VDD = 3.6V to 5.5V
13
ns
t4
SYNC to SCLK Rising
Edge Setup Time
VDD = 2.7V to 3.6V
0
ns
VDD = 3.6V to 5.5V
0
ns
t5
Data Setup Time
VDD = 2.7V to 3.6V
5
ns
VDD = 3.6V to 5.5V
5
ns
t6
Data Hold Time
VDD = 2.7V to 3.6V
4.5
ns
VDD = 3.6V to 5.5V
4.5
ns
t7
SCLK Falling Edge to
SYNC Rising Edge
VDD = 2.7V to 3.6V
0
ns
VDD = 3.6V to 5.5V
0
ns
t8
Minimum SYNC HIGH Time
VDD = 2.7V to 3.6V
50
ns
VDD = 3.6V to 5.5V
33
ns
NOTES: (1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation timing
diagram, below. (3) Maximum SCLK frequency is 30MHz at VDD = +3.6V to +5.5V and 20MHz at VDD = +2.7V to +3.6V.
TIMING CHARACTERISTICS(1, 2)
V
DD = +2.7V to +5.5V; all specifications –40°C to +105°C unless otherwise noted.
DAC8531E
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