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參數(shù)資料
| 型號： | DAC8512FSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 5V COMPLETE 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 98 |
| 設(shè)置時間： | 16µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.5mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 62.5k |
| 產(chǎn)品目錄頁面： | 786 (CN2011-ZH PDF) |
REV. A
–2–
DAC8512–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC PERFORMANCE
Resolution
N
Note 2
12
Bits
Relative Accuracy
INL
E Grade
–1
±1/4
+1
LSB
F Grade
–2
±3/4
+2
LSB
Differential Nonlinearity
DNL
No Missing Codes
–1
±3/4
+1
LSB
Zero-Scale Error
VZSE
Data = 000H
+1/2
+3
LSB
Full-Scale Voltage
VFS
Data = FFFH
3
E Grade
4.087
4.095
4.103
V
F Grade
4.079
4.095
4.111
V
Full-Scale Tempco
TCVFS
Notes 3, 4
16
ppm/
°C
ANALOG OUTPUT
Output Current
IOUT
Data = 800H
±5
±7mA
Load Regulation at Full Scale
LREG
RL = 402 to ∞, Data = 800H
1
3
LSB
Capacitive Load
CL
No Oscillation
4
500
pF
LOGIC INPUTS
Logic Input Low Voltage
VIL
0.8
V
Logic Input High Voltage
VIH
2.4
V
Input Leakage Current
IIL
10
A
Input Capacitance
CIL
10
pF
INTERFACE TIMING SPECIFICATIONS
1, 4
Clock Width High
tCH
30
10
ns
Clock Width Low
tCL
30
10
ns
Load Pulse Width
tLDW
20
ns
Data Setup
tDS
15
10
ns
Data Hold
tDH
15
5
ns
Clear Pulse Width
tCLRW
30
20
ns
Load Setup
tLD1
15
ns
Load Hold
tLD2
10
ns
Select
tCSS
30
ns
Deselect
tCSH
20
ns
AC CHARACTERISTICS
4
Voltage Output Settling Time
tS
To
±1 LSB of Final Value5
16
s
DAC Glitch
15
nV s
Digital Feedthrough
15
nV s
SUPPLY CHARACTERISTICS
Positive Supply Current
IDD
VIH = 2.4 V, VIL = 0.8 V, No Load
1.5
2.5
mA
VDD = 5 V, VIL = 0 V, No Load
0.5
1
mA
Power Dissipation
PDISS
VIH = 2.4 V, VIL = 0.8 V, No Load
7.5
12.5
mW
VDD = 5 V, VIL = 0 V, No Load
2.5
5
mW
Power Supply Sensitivity
PSS
V
DD =
±5%
0.002
0.004
%/%
NOTES
1All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
21 LSB = 1 mV for 0 V to +4.095 V output range.
3Includes internal voltage reference error.
4These parameters are guaranteed by design and not subject to production testing.
5The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
(@ VDD = +5.0 V
5%, –40 C
≤ T
A
≤ +85 C, unless otherwise noted)
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