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參數(shù)資料
| 型號(hào)： | DAC8426FSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT QUAD 10VREF 20SOIC |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 3µs |
| 位數(shù)： | 8 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 210mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 333k |
DAC8426
–8–
REV. C
a) Large Signal
b) Settling Time Response (Negative Transition)
c) Settling Time Response (Positive Transition)
Figure 3. Dynamic Response
The outputs can withstand an indefinite short-circuit to AGND
to typically 50 mA. The output may also be shorted to any volt-
age between VDD and VSS; however, care must be taken to not
exceed the device maximum power dissipation.
The amplifier’s emitter follower output stage consists of an in-
trinsic NPN bipolar transistor with a 400
A NMOS pull-down
current-source load connected to VSS. This circuit configuration
shown in Figure 4 enables the output amplifier to develop out-
put voltages very close to AGND. Only the negative supply of the
four output buffer amplifiers are connected to VSS. Operating
the DAC8426 from dual supplies (VDD = +15 V and VSS = –5 V)
improves negative going output settling time near zero volts.
When operating single supply (VDD = +15 V and VSS = 0 V) the
output sink current decreases as the output approaches zero
voltage. Within 200 mV of AGND (single-supply operation) the
internal sinking capability appears resistive at a value of approxi-
mately 1200
. The buffer amplifier output current and voltage
characteristics are plotted in Figure 5.
Test Conditions, All Photos:
VDD = +15 V
CREFOUT = 10 F
RL = 2 k
Digital Input Sequence 0, 255, 0
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