At VDD
參數(shù)資料
型號： DAC7802LU/1KG4
廠商： Texas Instruments
文件頁數(shù)： 17/23頁
文件大小： 0K
描述： IC DUAL 12BIT CMOS DAC 24-SOIC
產品培訓模塊： Data Converter Basics
標準包裝： 1,000
設置時間： 400ns
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉換器數(shù)目： 2
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應商設備封裝： 24-SOIC
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
DAC7800, 7801, 7802
3
SBAS005A
www.ti.com
AC PERFORMANCE
OUTPUT OP AMP IS OPA602.
At VDD = +5VDC, VREF A = VREF B = +10V, TA = +25°C, unless otherwise noted. These specifications are fully characterized but not subject to test.
NOTE: (1) Ensured but not tested.
DAC7800, 7801, 7802K
DAC7800, 7801, 7802L
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
OUTPUT CURRENT SETTLING TIME
To 0.01% of Full-Scale
0.4
0.8
s
RL = 100, CL = 13pF
DIGITAL-TO-ANALOG GLITCH IMPULSE
VREF A = VREF B = 0V
0.9
nV-s
RL = 100, CL = 13pF
AC FEEDTHROUGH
fVREF = 10kHz
–75
–72
dB
OUTPUT CAPACITANCE
DAC Loaded with All 0s
50
pF
DAC Loaded with All 1s
70
100
pF
CHANNEL-TO-CHANNEL ISOLATION
VREF A to IOUT B
fVREF A = 10kHz
–90
–94
dB
VREF B = 0V,
Both DACs Loaded with 1s
VREF B to IOUT A
fVREF B = 10kHz
–90
–101
dB
VREF A = 0V,
Both DACs Loaded with 1s
DIGITAL CROSSTALK
Full-Scale Transition
0.9
nV-s
RL = 100, CL = 13pF
Same specification as for DAC7800, 7801, and 7802K.
DAC7800
BLOCK DIAGRAM
DAC A
DAC B
DAC A Register
12
UPD B
I
AGND B
R
V
R
I
AGND A
UPD A
OUT B
FB B
REF B
REF A
FB A
OUT A
12
V
DD
9
DGND
10
15
16
14
13
4
3
2
1
6
DAC B Register
Bit 0
Bit 11
Bit 12
Bit 23
Control
Logic
and
Shift
Register
7
11
CLR
12
DAC7800
Data
In
5
CLK
8
CS
PIN CONFIGURATION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AGND A
CLK
UPD A
Data In
CS
AGND B
I
R
V
CLR
UPD B
DGND
OUT A
FB A
REF A
OUT B
DAC7800
I
R
V
FB B
REF B
DD
CLK
UPD A
UPD B
CS
CLR
FUNCTION
XXXX
0
All register contents set to 0’s (asynchronous).
X
1
X
No data transfer.
X
0
1
Input data is clocked into input register (location Bit 23) and previous data shifts.
X
0101
Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A.
X
1001
Input register bits 11 (LSB) - 0 (MSB) are loaded into DAC B.
X
0001
Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A, and input register bits 11 (LSB) - 0 (MSB)
are loaded into DAC B.
X = Don’t care.
means falling edge triggered.
LOGIC TRUTH TABLE
Top View
DIP
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