VDD to GND .................................." />
參數(shù)資料
型號: DAC7621EBG4
廠商: Texas Instruments
文件頁數(shù): 8/14頁
文件大?。?/td> 0K
描述: IC SNGL 12BIT PARALLEL D/A 20SSO
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 70
設(shè)置時間: 7µs
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 5mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極
采樣率(每秒): 143k
3
DAC7621
PIN CONFIGURATION
Top View
SSOP
VDD to GND .......................................................................... –0.3V to 6V
Digital Inputs to GND .............................................. –0.3V to VDD + 0.3V
VOUT to GND ........................................................... –0.3V to VDD + 0.3V
Power Dissipation ........................................................................ 325mW
Thermal Resistance,
θ
JA ........................................................... 150°C/W
Maximum Junction Temperature .................................................. +150
°C
Operating Temperature Range ...................................... –40
°C to +85°C
Storage Temperature Range ....................................... –65
°C to +150°C
Lead Temperature (soldering, 10s) .............................................. +300
°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS(1)
PIN DESCRIPTIONS
PIN
LABEL
DESCRIPTION
1
CLR
Reset. Resets the DAC register to zero. Active
LOW. Asynchronous input.
2VDD
Postive Power Supply
3VOUT
DAC Output Voltage
4
AGND
Analog Ground
5
DGND
Digital Ground
6
DB11
Data Bit 11, MSB
7
DB10
Data Bit 10
8
DB9
Data Bit 9
9
DB8
Data Bit 8
10
DB7
Data Bit 7
11
DB6
Data Bit 6
12
DB5
Data Bit 5
13
DB4
Data Bit 4
14
DB3
Data Bit 3
15
DB2
Data Bit 2
16
DB1
Data Bit 1
17
DB0
Data Bit 0, LSB
18
R/W
Read and Write Control
19
CS
Chip Select. Active LOW.
20
LOADDAC
Loads the internal DAC register. The DAC register
is a transparent latch and is transparent when
LOADDAC is LOW (regardless of the state of CS or
CLK).
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE
DIFFERENTIAL
SPECIFICATION
PACKAGE
ACCURACY
NONLINEARITY
TEMPERATURE
DRAWING
ORDERING
TRANSPORT
PRODUCT
(LSB)
RANGE
PACKAGE
NUMBER(1)
NUMBER(2)
MEDIA
DAC7621E
±2
±1
–40
°C to +85°C
20-Lead SSOP
334
DAC7621E
Rails
""
"
""
DAC7621E/1K
Tape and Reel
DAC7621EB
±1
–40
°C to +85°C
20-Lead SSOP
334
DAC7621EB
Rails
""
"
""
DAC7621EB/1K
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7621E/1K” will get a single
1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
V
DD
V
OUT
AGND
DGND
DB11 (MSB)
DB10
DB9
DB8
DB7
LOADDAC
CS
R/W
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DAC7621E
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