參數(shù)資料
型號: DAC7512N/250
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 12 us SETTLING TIME, 12-BIT DAC, PDSO6
封裝: SOT-23, 6 PIN
文件頁數(shù): 4/16頁
文件大?。?/td> 393K
代理商: DAC7512N/250
DAC7512
12
SBAS156
THEORY OF OPERATION
D/A SECTION
The DAC7512 is fabricated using a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Since there is no reference input pin, the
power supply (VDD) acts as the reference. Figure 1 shows a
block diagram of the DAC architecture.
be as high as 30MHz, making the DAC7512 compatible
with high-speed DSPs. On the sixteenth falling edge of the
serial clock, the last data bit is clocked in and the pro-
grammed function is executed (i.e., a change in DAC regis-
ter contents and/or a change in the mode of operation).
At this point, the SYNC line may be kept LOW or brought
HIGH. In either case, it must be brought HIGH for a
minimum of 33ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence.
Since the SYNC buffer draws more current when the SYNC
signal is HIGH than it does when it is LOW, SYNC should
be idled LOW between write sequences for lowest power
operation of the part. As mentioned above, however, it must
be brought HIGH again just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 3). The
first two bits are “don’t cares”. The next two bits (PD1 and
PD0) are control bits that control which mode of operation
the part is in (normal mode or one of three power-down
modes). There is a more complete description of the various
modes in the Power-Down Modes section. The next 12 bits
are the data bits. These are transferred to the DAC register
on the sixteenth falling edge of SCLK.
The input coding to the DAC7512 is straight binary, so the
ideal output voltage is given by:
where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 4095.
RESISTOR STRING
The resistor string section is shown in Figure 2. It is simply
a string of resistors, each of value R. The code loaded into
the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier by
closing one of the switches connecting the string to the
amplifier. It is guaranteed monotonic because it is a string of
resistors.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-
rail voltages on its output which gives an output range of
0V to VDD. It is capable of driving a load of 2kW in parallel
with 1000pF to GND. The source and sink capabilities of the
output amplifier can be seen in the typical curves. The slew
rate is 1V/
s with a half-scale settling time of 8s with the
output unloaded.
SERIAL INTERFACE
The DAC7512 has a three-wire serial interface (SYNC,
SCLK and DIN), which is compatible with SPI, QSPI and
Microwire interface standards as well as most Digital Signal
Processors (DSPs). See the Serial Write Operation timing
diagram for an example of a typical write sequence.
The write sequence begins by bringing the SYNC line LOW.
Data from the DIN line is clocked into the 16-bit shift register
on the falling edge of SCLK. The serial clock frequency can
FIGURE 1. DAC7512 Architecture
FIGURE 2. Resistor String.
V
D
OUT
DD
=
4096
To Output
Amplifier
R
DAC Register
REF (+)
Resistor
String
REF(–)
Output
Amplifier
GND
V
DD
V
OUT
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DAC7512N/3K SERIAL INPUT LOADING, 12 us SETTLING TIME, 12-BIT DAC, PDSO6
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DAC7512N/3K SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO6
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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