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參數(shù)資料
| 型號： | DAC4815BP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | QUAD, PARALLEL, 8 BITS INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 151K |
| 代理商： | DAC4815BP |
7
DAC4815
PARAMETER
MINIMUM
t1—Address Valid to Write Setup Time
20ns
t2—Address Valid to Write Hold Time
10ns
t3—Data Setup Time
30ns
t4—Data Hold Time
10ns
t5—Chip Select to LE or Write
0ns
Setup Time
t6—Chip Select to LE or Write
0ns
Hold Time
t7—Write Pulse Width
40ns
t8—Clear Pulse Width
40ns
TIMING CHARACTERISTICS
+VL = +5V, TA = –40°C to +85°C.
NOTE: X = Don’t care.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1
LSB change in the output voltage when the input code
changes by 1 LSB. A differential nonlinearity specification
of
±1 LSB maximum guarantees monotonicity.
BIPOLAR ZERO ERROR
The output voltage for code 800HEX.
GAIN ERROR
The deviation of the output voltage span (V
MAX – VMIN)
from the ideal span of 20V – 1 LSB (bipolar mode). The gain
error is specified with and without the internal +10V refer-
ence error included.
OUTPUT SETTLING TIME
The time required for the output voltage to settle within a
percentage-of-full-scale error band for a full scale transition.
Settling to
±0.012% (1/2 LSB) is specified for the DAC4815.
DISCUSSION OF
SPECIFICATIONS
INPUT CODES
All digital inputs of the DAC4815 are TTL and 5V CMOS
compatible. Input codes for the DAC4815 are BOB (Bipolar
Offset Binary). See Figure 3 for
±10V bipolar connection.
INTEGRAL OR RELATIVE LINEARITY
This term, also know as end point linearity, describes the
transfer function of analog output to digital input code.
Integral linearity error is the deviation of the analog output
versus code transfer function from a straight line drawn
through the end points.
BIPOLAR OUTPUTS FOR SELECTED INPUT
DIGITAL INPUT
BIPOLAR (BOB)
FFFHEX
+Full Scale
800HEX
Zero
7FFHEX
Zero – 1 LSB
000HEX
–Full Scale
t
5
t
6
t
7
t
8
CS
LE, WR
CLR
0V
5V
0V
5V
NOTES: (1) All input signal rise and fall times are measured
from 10% to 90% of +5V. t = t = 5ns.
RF
IH
IL
2
t
1
t
3
t
4
t
2
0V
5V
DATA
A
0-A2
(2) Timing measurement reference level is V
+ V .
INTERFACE LOGIC TRUTH TABLE
CLR
LE
CS
WR
A2
A1
A0
FUNCTION
1
0
DAC A LS input register loaded with D7-D0(LSB)
1
0
1
DAC A MS input register loaded with D3(MSB)-D0
1
0
1
0
DAC B LS input register loaded with D7-D0(LSB)
1
0
1
DAC B MS input register loaded with D3(MSB)-D0
1
0
1
0
DAC C LS input register loaded with D7-D0(LSB)
1
0
1
0
1
DAC C MS input register loaded with D3(MSB)-D0
1
0
1
0
DAC D LS input register loaded with D7-D0(LSB)
1
0
1
DAC D MS input register loaded with D3(MSB)-D0
1
0
1
X
All DAC registers updated simultaneously from input registers
1
0
X
All DAC registers are transparent
1
X
1
X
No data transfer
1
X
1
X
No data transfer
0
X
Input registers cleared = 000HEX, DAC registers = 800HEX
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