參數(shù)資料
型號: DAC1401D125HL
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 14-bit DAC, up to 125 Msps
中文描述: PARALLEL, WORD INPUT LOADING, 0.043 us SETTLING TIME, 14-BIT DAC, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC. LQFP-48
文件頁數(shù): 17/25頁
文件大?。?/td> 359K
代理商: DAC1401D125HL
DAC1401D125_1
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
17 of 25
NXP Semiconductors
DAC1401D125
Dual 14-bit DAC, up to 125 Msps
10.3 Timing
The DAC1401D125 can operate at an update rate up to 125 Msps. This generates an
input data rate of 125 MHz in Dual port mode and 250 MHz in Interleaved mode. The
timing of the DAC1401D125 is shown in
Figure 18
.
The typical performances are measured at 50 % duty cycle but any timing within the limits
of the characteristics will not alter the performance.
A configuration resulting in the same timing for the signals WRTA/WRTB and
CLKA/CLKB, can be achieved either by synchronizing them or by connecting them
together.
The rising edge of the CLKA/CLKB signal can also be placed in a range from half a
period in front of the rising edge of the WRTA/WRTB signal to half a period minus 1 ns
after the rising edge of the WRTA/WRTB signal.
A typical set-up time of 0 ns and a hold time of 0.6 ns enable the DAC1405D125 to be
easily integrated into any application.
10.4 DAC transfer function
The full-scale output current for each DAC is the sum of the two complementary current
outputs:
(1)
The output current depends on the digital input data:
DATA
16384
Fig 18. Timing of the DAC1401D125
001aai937
t
su(i)
t
w(WRT)
DA13 to DA0/
DB13 to DB0
WRTA/
WRTB
CLKA/
CLKB
IOUTAP, IOUTAN/
IOUTBP, IOUTBN
t
d(clk)
t
w(CLK)
10 %
90 %
t
d
t
t
t
s
t
h(i)
I
O fs
)
I
IOUTP
I
IOUTN
+
=
I
IOUTP
I
O fs
)
---------------
×
=
I
IOUTN
I
O fs
)
16383
-----------------------------------------
DATA
(
)
16384
×
=
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