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參數(shù)資料
| 型號： | CYW150OXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK 440BX AGP 56SSOP |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 類型： | 時鐘/頻率合成器，擴展頻譜時鐘發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 時鐘，晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:33 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 150MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 管件 |
CYW150
........................ Document #: 38-07177 Rev. *B Page 5 of 14
Serial Data Interface
The CYW150 features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions. Upon power-up, the CYW150
initializes with default register settings, therefore the use of this
serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica-
tions, SDATA and SCLOCK are typically driven by two logic
outputs of the chipset. If needed, clock device register
changes are normally made upon system initialization. The
interface can also be used during system operation for power
management functions. Table 3 summarizes the control
functions of the serial data interface.
Operation
Data is written to the CYW150 in eleven bytes of eight bits
each. Bytes are written in the order shown in Table 4.
MAX
MIN
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
100
%
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
100
%
FREQUENCY
Figure 4. Typical Modulation Profile
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI and
system power. Examples are clock outputs to
unused PCI slots.
CPU Clock
Frequency Selection
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency transition
allows CPU frequency change under normal system
operation.
Spread Spectrum
Enabling
Enables or disables spread spectrum clocking.
For EMI reduction.
Output Three-state
Puts clock output into a high-impedance state.
Production PCB testing.
Test Mode
All clock outputs toggle in relation to X1 input,
internal PLL is bypassed. Refer to Table 5.
Production PCB testing.
(Reserved)
Reserved function for future device revision or
production device testing.
No user application. Register bit must be written as
0.
Table 4. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address 11010010
Commands the CYW150 to accept the bits in Data Bytes 0–7 for internal register
configuration. Since other devices may exist on the same common serial data bus,
it is necessary to have a specific slave address for each potential receiver. The
slave receiver address for the CYW150 is 11010010. Register setting will not be
made if the Slave Address is not correct (or is for an alternate slave receiver).
2
Command
Code
Don’t Care
Unused by the CYW150, therefore bit values are ignored (“Don’t Care”). This byte
must be included in the data write sequence to maintain proper byte allocation. The
Command Code Byte is part of the standard serial communication protocol and
may be used when writing to another addressed slave receiver on the serial data
bus.
3
Byte Count
Don’t Care
Unused by the CYW150, therefore bit values are ignored (“Don’t Care”). This byte
must be included in the data write sequence to maintain proper byte allocation. The
Byte Count Byte is part of the standard serial communication protocol and may be
used when writing to another addressed slave receiver on the serial data bus.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYW150OXCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Legacy-440BX AGP Refer to W150 DS RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CYW152-12G | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CYW15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYW15G0101DXB-BBC | 功能描述:電信線路管理 IC Sngl Ch XCVR COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYW15G0101DXB-BBI | 功能描述:電信線路管理 IC Sngl Ch XCVR IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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