參數(shù)資料
型號(hào)： CY8CLED03D01-56LTXI
廠商： Cypress Semiconductor Corp
文件頁(yè)數(shù)： 10/55頁(yè)
文件大?。?/td> 0K
描述： IC POWERPSOC 3CH 1A 56VQFN
特色產(chǎn)品： PowerPSoC? Embedded Power Controller
標(biāo)準(zhǔn)包裝： 260
系列： PowerPSoC® CY8CLED
核心處理器： M8C
芯體尺寸： 8-位
速度： 24MHz
連通性： DALI，DMX512，I²C，IrDA，SPI，UART/USART
外圍設(shè)備： LED，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 14
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤(pán)
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 698 (CN2011-ZH PDF)
配用： 428-2882-ND - KIT STARTER POWERPSOC LIGHTING
428-2281-ND - KIT EVAL POWERPSOC LIGHTING
428-2270-ND - KIT STARTER DEMO LIGHTING
其它名稱： 428-2924
CY8CLED04D01, CY8CLED04D02, CY8CLED04G01
CY8CLED03D01, CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
Document Number: 001-46319 Rev. *P
Page 18 of 55
10.2 In-Circuit Emulator
A low cost, high functionality in-circuit emulator (ICE) is available
for development support. This hardware has the capability to
program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PowerPSoC devices.
11. Designing with User Modules
The development process for the PowerPSoC device differs
from that of a traditional fixed function microprocessor. The
configurable power, analog, and digital hardware blocks give the
PowerPSoC architecture a unique flexibility that pays dividends
in managing specification change during development and by
lowering inventory costs. These configurable resources, called
PowerPSoC Blocks, have the ability to implement a wide variety
of user-selectable functions. The PowerPSOC development
process can be summarized in the following four steps:
1. Select components
2. Configure components
3. Organize and connect
4. Generate, Verify and debug
Select Components. In the chip-level view the components are
called “user modules”. User modules make selecting and
implementing peripheral devices simple and come in power,
analog, digital, and mixed signal varieties. The standard user
module library contains over 50 common peripherals such as
current sense amplifiers, PrISM, PWM, DMM, Floating Buck,
Boost, ADCs, DACs, Timers, Counters, UARTs, and other not so
common peripherals such as DTMF generators and Bi-Quad
analog filter sections.
Configure Components. Each of the components selected
establishes the basic register settings that implement the
selected function. They also provide parameters allowing
precise configuration to your particular application. For example,
a PWM User Module configures one or more digital PSoC
blocks, one for each 8 bits of resolution. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus.
The chip-level user modules are documented in datasheets that
are viewed directly in PSoC Designer. These datasheets explain
the internal operation of the component and provide
performance specifications. Each datasheet describes the use
of each user module parameter and other information needed to
successfully implement your design.
Organize and Connect. Signal chains can be built at the chip
level by interconnecting user modules to each other and the I/O
pins. In the chip-level view, perform the selection, configuration,
and routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug. When ready to test the hardware
configuration or move on to developing code for the project,
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high level user
module API functions.
The chip-level designs generate software based on your design.
The chip-level view provides application programming interfaces
(APIs) with high level functions to control and respond to
hardware events at run-time and interrupt service routines that
you can adapt as needed.
A complete code development environment allows development
and customization of your applications in C, assembly language,
or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you to define complex breakpoint events that
include monitoring address and data bus values, memory
locations, and external signals.
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