參數(shù)資料
型號: CY7C43666AV-15AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO
中文描述: 4K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128
文件頁數(shù): 27/40頁
文件大?。?/td> 644K
代理商: CY7C43666AV-15AC
CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 27 of 40
Notes:
42. If Port B size is word or byte, EFB is set LOW by the last word or byte Read from FIFO1, respectively.
43. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than t
SKEW1
, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
ENS
t
ENH
t
A
t
DS
W1
LOW
t
DH
HIGH
HIGH
FIFO1 Empty
LOW
LOW
W1
t
ENS
t
ENH
t
REF
t
REF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1
[43]
CLKA
CSA
W/RA
MBA
ENA
FFA/IRA
A
0
35
CLKB
EFB/ORB
CSB
MBB
RENB
B
0
17
EFB Flag Timing and First Data Read Fall Through when FIFO1 is
Empty (CY Standard Mode)
[42]
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