參數(shù)資料
型號(hào)： CY7C036AV-25AI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： SRAM
英文描述： 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
中文描述： 16K X 18 DUAL-PORT SRAM, 25 ns, PQFP100
封裝： PLASTIC, TQFP-100
文件頁(yè)數(shù)： 12/19頁(yè)
文件大?。?/td> 241K
代理商： CY7C036AV-25AI
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *E
Page 12 of 19
Notes:
32. R/W must be HIGH during all address transitions.
33. A write occurs during the overlap (t
or t
) of a LOW CE or SEM and a LOW UB or LB.
34. t
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
35. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t
) to allow the I/O drivers to turn off and data to be placed on
the bus for the required t
SD
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
PWE
.
36. To access RAM, CE = V
, SEM = V
.
37. To access upper byte, CE = V
, UB = V
, SEM = V
IH
.
To access lower byte, CE = V
, LB = V
, SEM = V
.
38. Transition is measured
±
500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
39. During this period, the I/O pins are in the output state, and input signals must not be applied.
40. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Switching Waveforms
(continued)
t
AW
t
WC
t
PWE
t
HD
t
SD
t
HA
CE
R/W
OE
DATAOUT
DATA IN
ADDRESS
t
HZOE
t
SA
t
HZWE
t
LZWE
Write Cycle No.1: R/W Controlled Timing
[32, 33, 34, 35]
[38]
[38]
[35]
[36, 37]
NOTE 39
NOTE 39
t
AW
t
WC
t
SCE
t
HD
t
SD
t
HA
CE
R/W
DATA IN
ADDRESS
t
SA
Write Cycle No. 2: CE Controlled Timing
[32, 33, 34, 40]
[36, 37]
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