參數(shù)資料
型號(hào)： CY7C007AV-25JC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： Safety Sign; Legend:Authorized Personnel Only; External Height:10"; External Width:14"; Body Material:Aluminum; Color:Red/White RoHS Compliant: NA
中文描述： 32K X 8 DUAL-PORT SRAM, 25 ns, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 7/20頁(yè)
文件大小： 301K
代理商： CY7C007AV-25JC
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 7 of 20
Switching Characteristics
Over the Operating Range
[15]
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE[16]
t
DOE
t
LZOE[17, 18, 19]
t
HZOE[17, 18, 19]
t
LZCE[17, 18, 19]
t
HZCE[17, 18, 19]
t
PU[19]
t
PD[19]
WRITE CYCLE
t
WC
t
SCE[16]
t
AW
t
HA
t
SA[16]
t
PWE
t
SD
t
HD
t
HZWE[18, 19]
t
LZWE[18, 19]
t
WDD[20]
t
DDD[20]
BUSY TIMING
[21]
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
Note:
15. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
16. To access RAM, CE=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
SCE
time.
17. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
18. Test conditions used are Load 3.
19. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing
with Busy waveform.
20. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
21. Test conditions used are Load 2.
Description
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-20
Min.
Max.
Unit
-25
Min.
Max.
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
20
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
3
3
20
12
25
13
3
3
12
15
3
3
12
15
0
0
20
25
Write Cycle Time
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
20
16
16
0
0
16
12
0
25
20
20
0
0
20
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
15
3
3
40
30
50
35
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
20
20
20
16
20
20
20
17
ns
ns
ns
ns
ns
5
5
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