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參數(shù)資料
| 型號： | CY28551LFXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK INTEL/AMD SIS VIA 64QFN |
| 標準包裝： | 260 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU，AMD CPU |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:23 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 托盤 |
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CY28551
....................Document #: 001-05675 Rev. *C Page 18 of 28
CLKREQ# Clarification
The CLKREQ# signals are active LOW inputs used to cleanly
stop and start selected SRC outputs. The outputs controlled
by CLKREQ# are determined by the settings in register bytes
10 and 11. The CLKREQ# signal is a debounced signal in that
its state must remain unchanged during two consecutive rising
edges of DIFC to be recognized as a valid assertion or
deassertion. (The assertion and deassertion of this signal is
absolutely asynchronous.)
CLKREQ# Assertion
All differential outputs that were stopped will resume normal
operation in a glitch-free manner. The maximum latency from
the deassertion to active outputs is between 2 and 6 PCIEX
clock periods (2 clocks are shown) with all CLKREQ# outputs
resuming simultaneously. If the CLKREQ# drive mode is
tri-state, all stopped PCIEX outputs must be driven HIGH
within 10 ns of CLKREQ# deassertion to a voltage greater than
200 mV.
CLKREQ# Deassertion
The impact of asserting the CLKREQ# pins is that all DIF
outputs that are set in the control registers to stoppable via
assertion of CLKREQ# are to be stopped after their next
transition. When the control register CLKREQ# drive mode bit
is programmed to '0', the final state of all stopped PCIEX
signals is PCIEXT clock = HIGH and PCIEXC = LOW. There
will be no change to the output drive current values. SRCT will
be driven HIGH with a current value equal 6 x Iref. When the
control register CLKREQ# drive mode bit is programmed to '1',
the final state of all stopped DIF signals is LOW; both PCIEXT
clock and PCIEXC clock outputs will not be driven.
Tsu _ p c i_stp# >
10ns
PC I_ STP#
PC I_ F
PC I
P C IE X 10 0M H z
Figure 7. PCI_STP# Assertion
PCI_STP#
PCI_F
PCI
PCIEX 100MHz
Tdrive_PCIEX <15 ns
Figure 8. PCI_STP# Deassertion
P CIEXC (stoppable)
PC IE XT(stoppable)
P C IEX C (free running )
PC IE XT(free running)
PE _R EQ #
Tdrive_PE_R EQ #
< 10 ns
Figure 9. CLKREQ# Deassertion
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28551LFXC-3 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Universal System Clk Intel AMD SiS Via RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28551LFXC-3T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Universal System Clk Intel AMD SiS Via RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28551LFXCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Universal System Clk Intel AMD SiS Via RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY2862-000 | 制造商:TE Connectivity 功能描述:82A0111-4-9-G110 |
| CY2863-000 | 制造商:TE Connectivity 功能描述:82A0111-8-9-G110 - Bulk |
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