參數(shù)資料
型號(hào): CY28547LFXC
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 21/24頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK CK505/410M INTEL 72QFN
標(biāo)準(zhǔn)包裝: 240
類型: 時(shí)鐘/頻率發(fā)生器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: LVTTL,晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 3:23
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 200MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 72-QFN(10x10)
包裝: 托盤
CY28547
.......................Document #: 001-05103 Rev *B Page 6 of 24
2
1
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disabled, 1 = Enabled
1
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disabled, 1 = Enabled
0
1
SRC[T/C]0
/LCD_96_100M[T/C]
SRC[T/C]0/LCD_96_100M[T/C] Output Enable
0 = Disabled, 1 = Enabled
Byte 2 Control Register 2
Bit
@Pup
Name
Description
7
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6
1
27M NSS/DOT_96[T/C]
27M Non-spread and DOT_96 MHz Output Enable
0 = Disable, 1 = Enabled
5
1
48M
48-MHz Output Enable
0 = Disabled, 1 = Enabled
4
1
REF0
REF0 Output Enable
0 = Disabled, 1 = Enabled
3
1
REF1
REF1 Output Enable
0 = Disabled, 1 = Enabled
2
1
CPU[T/C]1
CPU[T/C]1 Output Enable
0 = Disabled, 1 = Enabled
1
CPU[T/C]0
CPU[T/C]0 Output Enable
0 = Disabled, 1 = Enabled
0
1
CPU, SRC, PCI, PCIF
Spread Enable
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 3 Control Register 3
Bit
@Pup
Name
Description
7
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
6
1
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
5
1
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
4
1
PCI1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
3
1
RESERVED
2
1
RESERVED
1
CPU[T/C]2/SRC[T/C]10 CPU[T/C]2/SRC[T/C]10 Output Enable
0 = Disabled, 1 = Enabled
0
1
RESERVED
Byte 4 Control Register 4
Bit
@Pup
Name
Description
7
0
SRC7
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6
0
SRC6
Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
5
0
SRC5
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
4
0
SRC4
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 1 Control Register 1 (continued)
Bit
@Pup
Name
Description
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