- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8999 > CY28508OXCT (Silicon Laboratories Inc)IC CLOCK SSCG 3DIFF PAIR 28SSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | CY28508OXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SSCG 3DIFF PAIR 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 333.3MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)
CY28508
........................ Document #: 38-07534 Rev. *F Page 5 of 13
Byte 3: Dial-a-Frequency Control Register N1 [default = 224.70 MHz, N = 86d, ODSEL = 1]
Bit
@Pup
Description
7
0
Reserved, set = 0.
61
N6, MSB
50
N5
41
N4
30
N3
21
N2
11
N1
00
N0, LSB
Byte 4: Dial-a-Frequency Control Register M1 [default = 224.70 MHz, M = 49d, ODSEL = 1]
Bit
@Pup
Description
7
1
Reserved, set = 1.
6
1
SWODSEL: Output divider select. 0 = /2, 1 = /3.
Changing the output divider causes large instantaneous changes in the CPU pulse width and
should only be changed before system operation is to occur.
5
1
M5 MSB.
41
M4
30
M3
20
M2
10
M1
0
1
M0, LSB.
Byte 5: Dial-a-Frequency Control Register N2 – Only Bit 7 is Used by the CY28508
Bit
@Pup
Description
7
0
UP/DN pulse width limit. During Smooth-Track, the bandwidth hence the slew rate is controlled through
limiting the pulse width of the UP/DN pulse outputs of the phase detector going to the charge pump. The
default is 0 = 20 ns and can be programmed to 1 = 40 ns, which will increase the slew rate.
6
0
Reserved, set = 0.
5
1
Reserved, set = 1.
4
1
Reserved, set = 1.
3
0
Reserved, set = 0.
2
0
Reserved, set = 0.
1
0
Reserved, set = 0.
0
Reserved, set = 0.
Byte 6: Dial-a-Frequency Control Register M2 – Only Bits 6 and 7 are Used by the CY28508
Bit
@Pup
Description
7
1
FSEL Control: 1 = HW FSEL, 0 = SW FSEL
6
1
SW FSEL: 0 = SW MN0 select, 1 = SW MN1 select. Only valid when B6b7 = 0.
5
1
Reserved, set = 1.
4
1
Reserved, set = 1.
3
0
Reserved, set = 0.
2
0
Reserved, set = 0.
1
0
Reserved, set = 0.
0
Reserved, set = 0.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-JTF-MZ-F2 | CONVERTER MOD DC/DC 72V 25W |
| LTC2601CDD-1#PBF | IC DAC 16BIT R-R 10-DFN |
| VI-JT4-MZ-F4 | CONVERTER MOD DC/DC 48V 25W |
| AD5313ARUZ | IC DAC 10BIT DUAL R-R 16-TSSOP |
| VI-JT4-MZ-F3 | CONVERTER MOD DC/DC 48V 25W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28510 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Peripheral I/O Clock Generator |
| CY28510OC | 制造商:Rochester Electronics LLC 功能描述:PERIPHERAL I/O CLOCK GENERATOR - Bulk |
| CY28510OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Peripheral I/O Clock Generator |
| CY28512ZC-2 | 制造商:Cypress Semiconductor 功能描述: |
| CY28512ZC-2T | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。