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參數(shù)資料
| 型號： | CY28409OCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK CK409GRANTSDALE 56TSSOP |
| 標準包裝： | 1,000 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:21 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
CY28409
........................Document #: 38-07445 Rev. *D Page 9 of 16
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 1.8 ms.
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped after being sampled by two
rising edges of the internal CPUT clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
There is no change to the output drive current values during
the stopped state. The CPUT is driven HIGH with a current
value equal to (Mult 0 ‘select’) x (Iref), and the CPUC signal
will not be driven. Due to the external pull-down circuitry,
CPUC will be LOW during this stopped state.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
REF
Tdrive_PWRDN#
<300
s, >200 mV
PD#
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
SRCT 100MHz
Tstable
<1.8 ms
Figure 4. Power-down Deassertion Timing Waveform
CPU_STP#
CPUT
CPUC
Figure 5. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPU Internal
Tdrive_CPU_STP#, 10 ns > 200 mV
Figure 6. CPU_STP# Deassertion Waveform
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28409OCXT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28409OXC | 功能描述:時鐘合成器/抖動清除器 SysClk Intel Grntsdl 865 and 875 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28409OXCT | 功能描述:時鐘合成器/抖動清除器 SysClk Intel Grntsdl 865 and 875 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28409ZC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28409ZCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
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