參數(shù)資料
型號: CY28346OXC
廠商: Silicon Laboratories Inc
文件頁數(shù): 2/19頁
文件大?。?/td> 0K
描述: IC CLOCK DIFF OUT CK408 56SSOP
標準包裝: 26
類型: *
PLL:
輸入: 晶體
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:19
差分 - 輸入:輸出: 無/是
頻率 - 最大: 200MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: *
封裝/外殼: *
供應商設備封裝: *
包裝: *
其它名稱: SLCY28346OXC
CY28346
......................Document #: 38-07331 Rev. *C Page 10 of 19
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tsetup) (see
Figure 14.) The PCI_F (0:2) clocks will not be affected by this
pin if their control bits in the SMBus register are set to allow
them to be free running.
Table 7. Cypress Clock Power Management Truth Table
B0b6
B1b6
PD#
CPU_STP# Stoppable CPUT
Stoppable
CPUC
Non-Stop CPUT
Non-Stop CPUC
0
1
Running
0
1
0
Iref x6
Running
0
1
Iref x2
LOW
Iref x2
LOW
0
Iref x2
LOW
Iref x2
LOW
0
1
Running
0
1
0
Hi-Z
Running
0
1
0
1
Hi-Z
0
1
0
Hi-Z
1
0
1
Running
1
0
1
0
Iref x6
Running
1
0
1
Hi-Z
1
0
Hi-Z
1
Running
1
0
Hi-Z
Running
1
0
1
Hi-Z
1
0
Hi-Z
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 10. CPU_STP# Deassertion Waveform
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