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參數(shù)資料
| 型號(hào)： | CY28329ZXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK CK408B PLUMAS 56SSOP |
| 標(biāo)準(zhǔn)包裝： | 35 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:24 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 133MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
| 其它名稱： | SLCY28329ZXC |
CY28329
....................... Document #: 38-07040 Rev. *E Page 2 of 16
Pin Description
Name
Pins
Description
REF
56
3.3V 14.318 MHz clock output
XTAL_IN
2
14.318 MHz crystal input
XTAL_OUT
3
14.318 MHz crystal input
CPU, CPU [0:3]#
44, 45, 48, 49,
51, 52, 53, 54
Differential CPU clock outputs
3V66_0
33
3.3V 66 MHz clock output
3V66_1/VCH
35
3.3V selectable through SMBus to be 66 MHz or 48 MHz
66IN/3V66_5
24
66 MHz input to buffered 66BUFF and PCI or 66 MHz clock from internal VCO
66BUFF [0:2]
/3V66 [2:4]
21, 22, 23
66 MHz buffered outputs from 66Input or 66 MHz clocks from internal VCO
PCI_F [0:2]
5, 6, 7,
33 MHz clocks divided down from 66Input or divided down from 3V66
PCI [0:6]
10, 11, 12, 13, 16,
17, 18
PCI clock outputs divided down from 66Input or divided down from 3V66
USB
39
Fixed 48 MHz clock output
DOT
38
Fixed 48 MHz clock output
S2
40
Special 3.3V 3-level input for Mode selection
S1
55
3.3V LVTTL inputs for CPU frequency selection
IREF
42
A precision resistor is attached to this pin which is connected to the internal current
reference
MULT0
43
3.3V LVTTL input for selecting the current multiplier for the CPU outputs
PD#
25
3.3V LVTTL input for Power_Down# (active LOW). Do not add any decoupling capac-
itors. Use an external 1.0-K
pull-up resistor.
PCI_STOP#
34
3.3V LVTTL input for PCI_STOP# (active LOW)
VTTPWRGD#
28
3.3V LVTTL input is a level-sensitive strobe used to determine when S[1:2] and
MULT0 inputs are valid and OK to be sampled (Active LOW). Once VTTPWRGD# is
sampled LOW, the status of this output will be ignored.
SDATA
29
SMBus-compatible SDATA
SCLK
30
SMBus-compatible Sclk
VDD_REF,
VDD_PCI,
VDD_3V66,
VDD_48 MHz,
VDD_CPU
1, 8, 14, 19, 32,
37, 46, 50
3.3V power supply for outputs
VDD_CORE
26
3.3V power supply for PLL
GND_REF,
GND_PCI,
GND_3V66,
GND_IREF,
VDD_CPU
4, 9, 15, 20, 31,
36, 41, 47
Ground for outputs
GND_CORE
27
Ground for PLL
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