參數(shù)資料
型號： CY28323OXC
廠商： Silicon Laboratories Inc
文件頁數(shù)： 3/21頁
文件大?。?/td> 0K
描述： IC CLOCK BROOKDALE GPENT4 48SSOP
標(biāo)準(zhǔn)包裝： 30
類型： 時鐘/頻率發(fā)生器
PLL： 是
主要目的： Intel CPU 服務(wù)器
輸入： 晶體
輸出： HCSL，LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:21
差分 - 輸入:輸出： 無/是
頻率 - 最大： 248MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 管件
CY28323PVC
..Document #: 38-07004 Rev. *B Page Page 11 of 21 of 21
Bit 6
--
ROCV_FREQ_M6
If ROCV_FREQ_SEL is set, the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be
use to determine the recovery CPU output frequency.when
a Watchdog timer time-out occurs.
The setting of FS_Override bit determines the frequency
ratio for CPU and other output clocks. When the
FS_Override bit is cleared, the same frequency ratio stated
in the Latched FS[4:0] register will be used. When it is set,
the frequency ratio stated in the SEL[4:0] register will be
used.
0
Bit 5
--
ROCV_FREQ_M5
0
Bit 4
--
ROCV_FREQ_M4
0
Bit 3
--
ROCV_FREQ_M3
0
Bit 2
--
ROCV_FREQ_M2
0
Bit 1
--
ROCV_FREQ_M1
0
Bit 0
--
ROCV_FREQ_M0
0
Data Byte 12 (continued)
Bit
Pin#
Name
Pin Description
Power On
Default
Data Byte 13
Bit
Pin#
Name
Pin Description
Power On
Default
Bit 7
--
CPU_FSEL_N7
If Prog_Freq_EN is set, the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to
determine the CPU output frequency. The new frequency
will start to load whenever CPU_FSELM[6:0] is updated.
The setting of the FS_Override bit determines the
frequency ratio for CPU and other output clocks. When it is
cleared, the same frequency ratio stated in the Latched
FS[4:0] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
0
Bit 6
--
CPU_FSEL_N6
0
Bit 5
--
CPU_FSEL_N5
0
Bit 4
--
CPU_FSEL_N4
0
Bit 3
--
CPU_FSEL_N3
0
Bit 2
--
CPU_FSEL_N2
0
Bit 1
--
CPU_FSEL_N1
0
Bit 0
--
CPU_FSEL_N0
0
Data Byte 14
Bit
Pin#
Name
Pin Description
Power On
Default
Bit 7
--
Pro_Freq_EN
Programmable output frequencies enabled
0 = disabled
1 = enabled
0
Bit 6
--
CPU_FSEL_M6
If Prog_Freq_EN is set, the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to
determine the CPU output frequency. The new frequency
will start to load whenever CPU_FSELM[6:0] is updated.
The setting of the FS_Override bit determines the
frequency ratio for CPU and other output clocks. When it is
cleared, the same frequency ratio stated in the Latched
FS[4:0] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
0
Bit 5
--
CPU_FSEL_M5
0
Bit 4
--
CPU_FSEL_M4
0
Bit 3
--
CPU_FSEL_M3
0
Bit 2
--
CPU_FSEL_M2
0
Bit 1
--
CPU_FSEL_M1
0
Bit 0
--
CPU_FSEL_M0
0
Data Byte 15
Bit
Pin#
Name
Pin Description
Power On
Default
Bit 7
--
Reserved
0
Bit 6
--
Reserved
0
Bit 5
--
Reserved
0
Bit 4
--
Reserved
0
Bit 3
--
Reserved
0
Bit 2
--
Reserved
0
Bit 1
--
Vendor Test Mode
Reserved. Write with “1”
1
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參數(shù)描述
CY28323OXCT 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Brookdale RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
CY28323PVC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY28324 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Intel Pentium 4 CPU and Chipsets
CY28324_02 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets
CY28324PVC 制造商:Cypress Semiconductor 功能描述:PLL Frequency Generator Dual 48-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:- Bulk
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