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CY2037
2
Functional Description
The CY2037 is an EPROM programmable, high accuracy,
PLL-based die designed for the crystal oscillator market. The
die attaches directly to a low-cost 10–30 MHz crystal and can
be packaged into 4-pin through-hole or surface mount packag-
es. The oscillator devices can be stocked as blank parts and
custom frequencies programmed in-package at the last stage
before shipping. This enables fast-turn manufacture of custom
and standard crystal oscillators without the need for dedicated,
expensive crystals.
The CY2037 contains an on-chip oscillator and an unique os-
cillator tuning circuit for fine-tuning of the output frequency. The
crystal C
load
can be selectively adjusted by programming a set
of seven EPROM bits. This feature can be used to compensate
for crystal variations or to obtain a more accurate synthesized
frequency.
The CY2037 uses EPROM programming with a simple 2-wire,
4-pin interface that includes V
SS
and V
DD
. Clock outputs can
be generated up to 133 MHz at 5V or up to 100 MHz at 3.3V.
The entire configuration can be re-programmed one time al-
lowing programmed inventory to be altered or reused.
The CY2037 PLL die has been designed for very high resolu-
tion. It has a 12 bit feedback counter multiplier and a 10 bit
reference counter divider. This enables the synthesis of highly
accurate and stable output clock frequencies with zero or low
PPM error. The clock can be further modified by eight output
divider options of 1, 2, 4, 8, 16, 32, 64 and 128. The divider
input can be selected as either the PLL or crystal oscillator
output providing a total of sixteen separate output options. For
further flexibility, the ouput is selectable between TTL and
CMOS duty cycle levels.
The CY2037A and CY2037-2 also contain flexible power man-
agement controls. These parts include both PWR_DWN and
OE features with integrated pull-up resistors. The PWR_DWN
and OE modes have an additional setting to determine timing
(asynchronous or synchronous) with respect to the output sig-
nal. When PWR_DWN or OE modes are enables, CLKOUT is
pulled low by a weak pull down. The weak pull down is easily
overdriven by another active CLKOUT for applications that re-
quire multiple CLKOUTs on a single signal path.
Controlled rise and fall times, unique output driver circuits, and
innovative circuit layout techniques enable the CY2037 to have
low jitter and accurate outputs making it suitable for most PC,
networking and consumer applications
DieConfiguration
CY2037 Logic Block Diagram
V
DD
Top View
V
SS
V
DD
X
G
PD/OE
or FS
CLKOUT
V
SS
X
G
PD/OE
or FS
X
D
CONFIGURATION
EPROM
CRYSTAL
CLKOUT
/ 1, 2, 4, 8, 16, 32, 64, 128
N/C / Xx
[1]
X
D
N/C
OSCILLATOR
1
2
3
4
5
6
7
8
9
11
MUX
HIGH
ACCURACY
PLL
N/C
10
7C803xx
Note:
1.
For Customers not bonding X
D
or X
G
pad to external pins, an alternative bonding option would be shorting the Xx pad to the X
D
pad.