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參數(shù)資料
| 型號： | CY143 |
| 英文描述： | 2K x 16 Dual-Port Static RAM(193.25 k) |
| 中文描述： | 2K × 16雙口靜態(tài)存儲器（193.25十一） |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 193K |
| 代理商： | CY143 |
CY7C133
CY7C143
5
Switching Characteristics
Over the Operating Range
[6]
Parameter
READ CYCLE
Description
7C133-25
7C143-25
Min.
7C133-35
7C143-35
Min.
7C133-55
7C143-55
Min.
Unit
Max.
Max.
Max.
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
6.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
/I
and 30-pF load capacitance.
7.
AC Test Conditions use V
= 1.6V and V
= 1.4V.
8.
At any given temperature and voltage condition for any given device, t
is less than t
and t
is less than t
.
9.
t
, t
LZWE
, t
HZOE
, t
LZOE
, t
HZCE
and t
HZWE
are tested with C
L
= 5 pF as in part (b) of AC Test Loads
.
Transition is measured ±500 mV from steady state
voltage.
10. This parameter is guaranteed but not tested.
11. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Read Cycle Time
Address to Data Valid
[7]
25
35
55
ns
25
35
55
ns
Data Hold from Address Change
CE LOW to Data Valid
[7]
OE LOW to Data Valid
[7]
OE LOW to Low Z
[8, 9,10]
OE HIGH to High Z
[8, 9,10]
CE LOW to Low Z
[8, 9,10]
CE HIGH to High Z
[8, 9,10]
CE LOW to Power-Up
[10]
CE HIGH to Power-Down
[10]
0
0
0
ns
25
35
55
ns
20
25
30
ns
3
3
3
ns
15
20
25
ns
3
5
5
ns
15
20
20
ns
0
0
0
ns
25
25
25
ns
Write Cycle Time
25
35
55
ns
CE LOW to Write End
20
25
40
ns
Address Set-Up to Write End
20
25
40
ns
Address Hold from Write End
2
2
2
ns
Address Set-Up to Write Start
0
0
0
ns
R/W Pulse Width
20
25
35
ns
Data Set-Up to Write End
15
20
20
ns
Data Hold from Write End
R/W LOW to High Z
[9,10]
R/W HIGH to Low Z
[9,10]
0
0
0
ns
15
20
20
ns
0
0
0
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY1461-000 | 制造商:TE Connectivity 功能描述:55PC0241-12-2/4/5/6CS2502 |
| CY14A | 功能描述:晶體 14.31818MHz Series 0C +70C RoHS:否 制造商:AVX 頻率:26 MHz 容差: 頻率穩(wěn)定性:50 PPM 負載電容:8 pF 端接類型:SMD/SMT 封裝 / 箱體:1210 (3225 metric) 工作溫度范圍:- 40 C to + 150 C 尺寸:2.5 mm W x 3.2 mm L x 0.85 mm H 封裝:Reel |
| CY14AC | 功能描述:晶體 14.31818MHz 18pF 0C +70C RoHS:否 制造商:AVX 頻率:26 MHz 容差: 頻率穩(wěn)定性:50 PPM 負載電容:8 pF 端接類型:SMD/SMT 封裝 / 箱體:1210 (3225 metric) 工作溫度范圍:- 40 C to + 150 C 尺寸:2.5 mm W x 3.2 mm L x 0.85 mm H 封裝:Reel |
| CY14ACS | 功能描述:晶體 14.31818MHz 18pF 0C +70C RoHS:否 制造商:AVX 頻率:26 MHz 容差: 頻率穩(wěn)定性:50 PPM 負載電容:8 pF 端接類型:SMD/SMT 封裝 / 箱體:1210 (3225 metric) 工作溫度范圍:- 40 C to + 150 C 尺寸:2.5 mm W x 3.2 mm L x 0.85 mm H 封裝:Reel |
| CY14ACSMD | 功能描述:晶體 14.31818MHz 18pF 0C +70C RoHS:否 制造商:AVX 頻率:26 MHz 容差: 頻率穩(wěn)定性:50 PPM 負載電容:8 pF 端接類型:SMD/SMT 封裝 / 箱體:1210 (3225 metric) 工作溫度范圍:- 40 C to + 150 C 尺寸:2.5 mm W x 3.2 mm L x 0.85 mm H 封裝:Reel |
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