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參數(shù)資料
| 型號： | CXD2411R |
| 英文描述： | Signal Generator for LCD |
| 中文描述： | 信號發(fā)生器的液晶顯示器 |
| 文件頁數(shù)： | 14/25頁 |
| 文件大?。?/td> | 1286K |
| 代理商： | CXD2411R |
–14–
CXD2403AR
Variable Range from the Center of Sync Signal to Hst Rise Timing
HP4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
HP3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
HP2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
HP1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
108CLK (10.7μs)
106CLK
104CLK
102CLK
100CLK
98CLK
96CLK
94CLK
92CLK
90CLK
88CLK
86CLK
84CLK
82CLK
80CLK
78CLK
(9.4μs)
(7.8μs)
HP1 to HP4 pins can be used to vary the
interval from the center of sync signal to HST
rise as shown in the left table.
Internal preset:
NTSC (typ.):
PAL (typ.):
1001 (90CLK)
1001 (90CLK)
1000 (92CLK)
4.7μs
1.5μs
10.9μs
2.7μs
6.5μs
2μs
6.1μs
1.4μs
1.3μs
SYNC
BLK
HD
XCLP
Liquid Crystal Panel Driving Pulse Generation
HST, HCK1, HCK2, VST, VCK1, and VCK2 (EN, CLR
in LCX005 mode only) are generated for the liquid
crystal panel driver.
External Sample-and-Hold Pulse Generation
Timing pulses of external sample-and-hold circuit
SH1, SH2, and SH3 are generated.
AC Driving Pulse Generation
FRP is output for liquid crystal AC driving. Field
inverts when F/H input pin is High and line inverts when
Low. Polarity is not specified for each field. The point is
changed from VCK1 and VCK2 pulse change points
after 1 clock.
HD-Clamp Pulse Generation
HD pulse is output during horizontal BLK in order to
drive the backlight (fluorescent tube). Even during no
signal, raster screen with no screen noise can be
created synchronizing to the free running frequency.
XCLP is output for BF timing clamp pulse.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CXD24-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CXD2412AQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for LCD Panels |
| CXD24-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CXD2422R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CCD Camera Timing Generator |
| CXD2424R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for Progressive Scan CCD Image Sensor |
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