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參數(shù)資料
| 型號： | CS8416-CNZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 31/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RCVR DGTL 192KHZ 28QFN COMM |
| 標準包裝： | 490 |
| 類型： | 數(shù)字音頻接口接收器 |
| 應用： | 數(shù)字音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-QFN |
| 供應商設備封裝： | 28-QFN 裸露焊盤（5x5） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 配用： | 598-1017-ND - BOARD EVAL FOR CS8416 RCVR |
| 其它名稱： | 598-1723 |
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DS578F3
37
CS8416
1 – Higher Update Rate Phase Detector - Recovered master clock (RMCK) will have low in-band jitter, but
increased wide-band jitter. Use this setting for the best performance when the output is connected to a delta-
sigma digital-to-analog converter (DAC).
TRUNC
– Determines if the audio word length is set according to the incoming channel status data as de-
coded by the AUX[3:0] bits. The resulting word length in bits is 24 minus AUX[3:0].
Default = ‘0’
0 – Incoming data is not truncated.
1 – Incoming data is truncated according to the length specified in the channel status data.
Truncation occurs before the de-emphasis filter. TRUNC has no effect on output data if de-emphasis filter
is not used.
Reserved
– These bits may change state depending on the input audio data.
14.3 Control1 (01h)
SWCLK
- Lets OMCK determine RMCK, OSCLK, OLRCK when PLL loses lock
Default = ‘0’
0 - Disable automatic clock switching. RMCK runs at the VCO frequency (~750 kHz) on PLL Unlock.
1 - Enable automatic clock switching on PLL unlock. OMCK clock input is automatically output on RMCK on
PLL Unlock.
MUTESAO
- Mute control for the serial audio output port
Default = ‘0’
0 - SDOUT not muted.
1 – SDOUT muted (set to all zeros).
INT[1:0]
- Interrupt output pin (INT) control
Default = ‘00’
00 - Active high; high output indicates interrupt condition has occurred.
01 - Active low, low output indicates an interrupt condition has occurred.
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. Thus it is not recommended
to multiplex INT onto GPO2 in IC Control Port Mode since an external resistor is required on GPO2 to spec-
ify the AD2 bit of the chip address.
11 – Reserved.
HOLD[1:0]
– Determine how received audio sample is affected when a receive error occurs
Default = ‘00’
00 – hold last audio sample.
01 – replace the current audio sample with all zeros (mute).
10- do not change the received audio sample.
11 - reserved
76543210
SWCLK
MUTESAO
INT1
INT0
HOLD1
HOLD0
RMCKF
CHS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS8416-CNZ | 制造商:Cirrus Logic 功能描述:Receiver IC RoHS Compliant:Yes |
| CS8416-CNZR | 功能描述:音頻發(fā)送器、接收器、收發(fā)器 IC 192 kHz Digital Audio Receiver RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數(shù)量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
| CS8416-CS | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:192 kHZ DIGITAL AUDIO INTERFACE RECEIVER |
| CS8416-CSR | 制造商:Cirrus Logic 功能描述:- Tape and Reel |
| CS8416CSZ | 制造商:Cirrus Logic 功能描述: |
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