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參數(shù)資料
| 型號： | CS82C84A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 5V 25MHZ 20-PLCC |
| 標(biāo)準(zhǔn)包裝： | 690 |
| 類型： | 時鐘發(fā)生器，時鐘同步器，扇出配送 |
| PLL： | 無 |
| 輸入： | TTL |
| 輸出： | TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 25MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC |
| 包裝： | 管件 |
3
FN2974.3
December 6, 2005
Pin Description
SYMBOL
NUMBER
TYPE
DESCRIPTION
AEN1,
AEN2
3, 7
I
ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready
Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are
useful in system configurations which permit the processor to access two Multi-Master System Busses.
In non-Multi-Master configurations, the AEN signal inputs are tied true (LOW).
RDY1,
RDY2
4, 6
I
BUS READY (Transfer Complete). RDY is an active HIGH signal which is an indication from a device
located on the system data bus that data has been received, or is available RDY1 is qualified by AEN1
while RDY2 is qualified by AEN2.
ASYNC
15
I
READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization mode of
the READY logic. When ASYNC is low, two stages of READY synchronization are provided. When
ASYNC is left open or HIGH, a single stage of READY synchronization is provided.
READY
5
O
READY: READY is an active HIGH signal which is the synchronized RDY signal input. READY is
cleared after the guaranteed hold time to the processor has been met.
X1, X2
17, 16
I O
CRYSTAL IN: X1 and X2 are the pins to which a crystal is attached. The crystal frequency is 3 times
the desired processor clock frequency, (Note 1).
F/C
13
I
FREQUENCY/CRYSTAL SELECT: F/C is a strapping option. When strapped LOW. F/C permits the
processor’s clock to be generated by the crystal. When F/C is strapped HIGH, CLK is generated for the
EFI input, (Note 1).
EFI
14
I
EXTERNAL FREQUENCY IN: When F/C is strapped HIGH, CLK is generated from the input frequency
appearing on this pin. The input signal is a square wave 3 times the frequency of the desired CLK
output.
CLK
8
O
PROCESSOR CLOCK: CLK is the clock output used by the processor and all devices which directly
connect to the processor’s local bus. CLK has an output frequency which is 1/3 of the crystal or EFI
input frequency and a 1/3 duty cycle.
PCLK
2
O
PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is 1/2 that of CLK
and has a 50% duty cycle.
OSC
12
O
OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal to
that of the crystal.
RES
11
I
RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C84A provides a
Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper
duration.
RESET
10
O
RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its timing
characteristics are determined by RES.
CSYNC
1
I
CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C84As to be
synchronized to provide clocks that are in phase. When CSYNC is HIGH the internal counters are reset.
When CSYNC goes LOW the internal counters are allowed to resume counting. CSYNC needs to be
externally synchronized to EFI. When using the internal oscillator CSYNC should be hardwired to
ground.
GND
9
Ground
VCC
18
VCC: The +5V power supply pin. A 0.1F capacitor between VCC and GND is recommended for
decoupling.
NOTE:
1. If the crystal inputs are not used X1 must be tied to VCC or GND and X2 should be left open.
82C84A
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| CS82C84AZ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 PERIPH CLK GENERATOR 5V 25MHZ 20PLCC COM RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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