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參數(shù)資料
| 型號： | CS5526-BSZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 8/30頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 20BIT W/4BIT LATCH 20SSOP |
| 標準包裝： | 1,000 |
| 位數(shù)： | 20 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12.7mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
| 配用： | 598-1014-ND - EVAL BOARD FOR CS5526 |
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CS5525 CS5526
16
DS202F5
Charge Pump Drive
The CPD (Charge Pump Drive) pin of the convert-
ers can be used with external components (shown
in Figure 1) to develop an appropriate negative bias
voltage for the NBV pin. When CPD is used to gen-
erate the NBV, the NBV voltage is regulated with
an internal regulator loop referenced to VA+.
Therefore, any change on VA+ results in a propor-
tional change on NBV. With VA+ = 5 V, NBV’s
regulation is set proportional to VA+ at approxi-
mately -2.1 V.
Figure 3 illustrates a means of supplying NBV volt-
age from a -5 V supply. For ground based signals
with the instrumentation amplifier engaged (when
in the 25mV, 55mV, or 100mV ranges), the voltage
on the NBV pin should at no time be less negative
than -1.8 V or more negative than -2.5 V. To pre-
vent excessive voltage stress to the chip the NBV
voltage should not be more negative than -3.0 V.
The components in Figure 1 are the preferred com-
ponents for the CPD filter. However, smaller ca-
pacitors can be used with acceptable results. The
10 F ensures very low ripple on NBV. Intrinsic
safety requirements prohibit the use of electrolytic
capacitors. In this case, two 0.47 F ceramic capac-
itors in parallel can be used.
The CPD pin itself is a tri-state output and enters
tri-state whenever the converters are placed into the
Sleep Mode, Standby Mode, or when the charge
pump is disabled (when the Pump Disable bit, bit
D8 in the configuration register, is set). Once in tri-
state, the digital current can increase if this CPD
output floats near 1/2 digital supply. To ensure the
CPD pin stays near ground and to minimize the
digital current, add a 5M
resistor between it and
DGND (see Figure 1). If the resistor is left out, the
digital supply current may increase from 2
A to 10
A.
Voltage Reference
The CS5525/26 are specified for operation with a
2.5 V reference voltage between the VREF+ and
VREF- pins of the devices. For a single-ended ref-
erence voltage, such as the LT1019-2.5, the refer-
ence’s output is connected to the VREF+ pin of the
CS5525/26. The ground reference for the LT1019-
2.5 is connected to the VREF- pin.
The differential voltage between the VREF+ and
VREF- can be any voltage from 1.0 V up to 3.0 V,
however, the VREF- pin can not go below analog
ground.
Calibration
The CS5525/26 offer five different calibration
functions including self calibration and system cal-
ibration. However, after the CS5525/26 are reset,
they can perform measurements without being cal-
ibrated. In this case, the converters will utilize the
initialized values of the on-chip registers (Gain =
1.0, Offset = 0.0) to calculate output words for the
±100 mV range. Any initial offset and gain errors
in the internal circuitry of the chips will remain.
The gain and offset registers, which are used for
both self and system calibration, are used to set the
zero and full-scale points of the converter’s transfer
function. One LSB in the offset register is 2-24 pro-
portion of the input span (bipolar span is 2 times the
unipolar span). The MSB in the offset register de-
termines if the offset to be trimmed is positive or
negative (0 positive, 1 negative). The converters
can typically trim ±50 percent of the input span.
The gain register spans from 0 to (2 - 2-23). The
decimal equivalent meaning of the gain register is
where the binary numbers have a value of either
zero or one (b0 corresponds to the MSB). Refer to
Table
4 for details.
Db
02
0
b
12
1
–
b
22
2
–
… b
N2
N
–
++
+
b
i2
i
–
i
0
=
N
∑
==
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