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參數(shù)資料
| 型號： | CS5525-ASZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 9/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT W/4BIT LATCH 20SSOP |
| 標準包裝： | 1,000 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12.7mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
| 配用： | 598-1013-ND - EVAL BOARD FOR CS5525 |
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CS5525 CS5526
DS202F5
17
The offset and gain calibration steps each take one
conversion cycle to complete. At the end of the cal-
ibration step, the calibration control bits will be set
back to logic 0, and the DF (Done Flag) bit will be
set to a logic 1. For the combination self-calibra-
tion (CC2-CC0= 011; offset followed by gain), the
calibration will take two conversion cycles to com-
plete and will set the DF bit after the gain calibra-
tion is completed. The DF bit will be cleared any
time the data register, the offset register, the gain
register, or the setup register is read. Reading the
configuration register alone will not clear the DF
bit.
Self Calibration
The CS5525/26 offer both self offset and self gain
calibrations. For the self-calibration of offset in the
25 mV, 55 mV, and 100 mv ranges, the converter
internally ties the inputs of the instrumentation am-
plifier together and routes them to the AIN- pin as
shown in Figure 10. For proper self-calibration of
offset to occur in the 25 mV, 55 mV, and 100 mV
ranges, the AIN- pin must be at the proper com-
mon-mode-voltage (i.e. AIN- = 0V, NBV must be
between -1.8 V to -2.5 V). For self-calibration of
offset in the 1.0 V, 2.5 V, and 5 V ranges, the inputs
of the modulator are connected together and then
routed to the VREF- pin as shown in Figure 11.
For self-calibration of gain, the differential inputs
of the modulator are connected to VREF+ and
Table 3.
Table 4. Offset and Gain Registers
Offset Register
One LSB represents 2-24 proportion of the input span (bipolar span is 2 times unipolar span)
Offset and data word bits align by MSB (bit MSB-4 of offset register changes bit MSB-4 of data)
Gain Register
The gain register span is from 0 to (2-2-23). After Reset the MSB = 1, all other bits are 0.
MSB
LSB
Register
Sign
2-2
2-3
2-4
2-5
2-6
2-19
2-20
2-21
2-22
2-23
2-24
Reset (R)
0
000000
MSB
LSB
Register
20
2-1
2-2
2-3
2-4
2-5
2-18
2-19
2-20
2-21
2-22
2-23
Reset (R)
1
0
000000
≈
AIN+
AIN-
S1
OPEN
S2
CLOSED
+
-
X20
+
-
Figure 10. Self Calibration of Offset (Low Ranges).
AIN+
AIN-
S1
OPEN
+
-
X20
+
-
S2
OPEN
S4
CLOSED
VREF-
S3
CLOSED
Figure 11. Self Calibration of Offset (High Ranges).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CS5525-BP | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16 BIT / 20 BIT MULTI RANGE ADC WITH 4 BIT LATCH |
| CS5525-BS | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16 BIT / 20 BIT MULTI RANGE ADC WITH 4 BIT LATCH |
| CS5526 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16 BIT / 20 BIT MULTI RANGE ADC WITH 4 BIT LATCH |
| CS5526-000 | 制造商:TE Connectivity 功能描述:S200-1-01 - Bulk |
| CS5526-BP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 20-Bit Delta Sigma Multi-Range ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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