參數(shù)資料
型號(hào)： CS5364-CQZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 14/42頁(yè)
文件大?。?/td> 0K
描述： IC ADC 4CH 114DB 216KHZ 48-LQFP
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 24
采樣率（每秒）： 216k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 580mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
輸入數(shù)目和類型： 4 個(gè)差分，單極
產(chǎn)品目錄頁(yè)面： 755 (CN2011-ZH PDF)
配用： CDB5364-ND - EVALUATION BOARD FOR CS5364
其它名稱： 598-1088
DS625F4
21
CS5364
4.4
Master and Slave Operation
CS5364 operation depends on two clocks that are synchronously derived from MCLK: SCLK and LRCK/FS.
See Section 4.5 on page 22 for a detailed description of SCLK and LRCK/FS.
The CS5364 can operate as either clock master or clock slave with respect to SCLK and LRCK/FS. In Mas-
ter Mode, the CS5364 derives SCLK and LRCK/FS synchronously from MCLK and outputs the derived
clocks on the SCLK pin (pin 25) and the LRCK/FS pin (pin 24), respectively. In Slave Mode, the SCLK and
LRCK/FS are inputs, and the input signals must be synchronously derived from MCLK by a separate device
such as another CS5364 or a microcontroller. Figure 8 illustrates the clock flow of SCLK and LRCK/FS in
both Master and Slave Modes.
The Master/Slave operation is controlled through the settings of M1 and M0 pins in Stand-Alone Mode or
by the M[1] and M[0] bits in the Global Mode Control Register in Control Port Mode. See Section 4.6 on page
23 for more information regarding the configuration of M1 and M0 pins or M[1] and M[0] bits.
Figure 8. Master/Slave Clock Flow
4.4.1
Synchronization of Multiple Devices
To ensure synchronous sampling in applications where multiple ADCs are used, the MCLK and LRCK must
be the same for all CS5364 devices in the system. If only one master clock source is needed, one solution
is to place one CS5364 in Master Mode, and slave all of the other devices to the one master, as illustrated
in Figure 9. If multiple master clock sources are needed, one solution is to supply all clocks from the same
external source and time the CS5364 reset de-assertion with the falling edge of MCLK. This will ensure that
all converters begin sampling on the same clock edge.
Figure 9. Master and Slave Clocking for a Multi-Channel Application
ADC as
clock
master
Controller
LRCK/FS
SCLK
ADC as
clock
slave
Controller
LRCK/FS
SCLK
Master
ADC
Slave1
ADC
Slave2
ADC
Slave3
ADC
SCLK & LRCK/FS
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參數(shù)描述
CS5364-CQZR 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC IC 114dB 192kHz 4ch ADC w/TDM Intrfc RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝:
CS5364-DQZ 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC 114dB 192kHz 4-Ch ADC w/TDM Interface RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝:
CS5364-DQZR 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC IC 114dB 192kHz 4ch ADC w/TDM Intrfc RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝:
CS5366 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz, 6-Channel A/D Converter
CS5366_08 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz, 6-Channel A/D Converter
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