- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1908 > CP80C86-2Z (Intersil)IC CPU 16BIT 5V 8MHZ 40-PDIP PDF資料下載
參數(shù)資料
| 型號： | CP80C86-2Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 34/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPU 16BIT 5V 8MHZ 40-PDIP |
| 標準包裝： | 9 |
| 處理器類型： | 80C86 16-位 |
| 速度： | 8MHz |
| 電壓： | 4.5 ~ 5.5V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應商設備封裝： | 40-DIP |
| 包裝： | 管件 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當前第34頁第35頁第36頁第37頁
6
FN2957.3
January 9, 2009
HOLD
HLDA
31, 30
I
O
HOLD: indicates that another master is requesting a local bus “hold”. To be an acknowledged, HOLD
must be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge” (HLDA) in
the middle of a t4 or TI clock cycle. Simultaneously with the issuance of HLDA, the processor will float
the local bus and control lines. After HOLD is detected as being LOW, the processor will lower HLDA,
and when the processor needs to run another cycle, it will again drive the local bus and control lines.
HOLD is not an asynchronous input. External synchronization should be provided if the system cannot
otherwise guarantee the setup time.
Minimum Mode System (Continued)
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to minimum
mode are described; all other pin functions are as described in the following.
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
Maximum Mode System
The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are unique
to maximum mode are described in the following.
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
S0
S1
S2
26
27
28
O
STATUS: is active during t4, t1 and t2 and is returned to the passive state (1, 1, 1) during t3 or during
tW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate all memory
and I/O access control signals. Any change by S2, S1 or S0 during t4 is used to indicate the beginning
of a bus cycle, and the return to the passive state in t3 or tW is used to indicate the end of a bus cycle.
These signals are held at a high impedance logic one state during “grant sequence”.
S2
S1
S0
CHARACTERISTICS
0
Interrupt Acknowledge
0
1
Read I/O Port
0
1
0
Write I/O Port
011
Halt
1
0
Code Access
1
0
1
Read Memory
1
0
Write Memory
1
Passive
80C86
相關PDF資料 |
PDF描述 |
|---|---|
| CP82C50A-5Z | IC ASYNC COMM ELEMENT UART 40DIP |
| CP82C89 | IC ARBITER BUS 5V 8MHZ 20-DIP |
| CPC1465D | IC DC TERMINATION 16-SOIC |
| CPC1465M | IC SHDSL/ISDN DC TERM 16MLP |
| CPC2400E | MODULE MODEM 2400BAUD EMBEDDEDED |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CP80C86R2489 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| CP80C88 | 功能描述:微處理器 - MPU CPU 8/16BIT 5V 5MHZ 40PDIP COM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| CP80C88-2 | 功能描述:微處理器 - MPU CPU 8/16BIT 5V 8MHZ 40PDIP COM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| CP80C88-2Z | 功能描述:IC PWM CONTROLLER RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應商設備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| CP80C88R2489 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。