參數資料
型號: CP2120EK
廠商: Silicon Laboratories Inc
文件頁數: 11/24頁
文件大小: 0K
描述: KIT EVAL FOR CP2120
產品培訓模塊: CP21xx USB Bridge
標準包裝: 1
主要目的: 接口,SPI 至 I²C
嵌入式:
已用 IC / 零件: CP2120
次要屬性: LED 狀態(tài)指示器
已供物品: 板,文檔,電源適配器
其它名稱: 336-1325
CP2120
Rev. 0.4
19
7. Port I/O
The CP2120 offers eight general-purpose port pins that can be configured as output, input, or quasi-bidirectional
output by writing to the internal registers, IOCONFIG and IOCONFIG2. Pin state can be updated by writing to the
internal register, IOSTATE. Reading the IOSTATE Internal Register will return the current values of each port pin.
The port pin, EINT, can be configured as an edge-triggered interrupt source by writing to the EDGEINT Internal
Register. The EIT bit sets the interrupt to trigger upon a 0 to 1 or a 1 to 0 logic change on the pin. The bit, EIE,
enables the pin as an interrupt source.
Once the interrupt has been configured and enabled, the CP2120 will pull the INT pin low when the port pin's logic
value switches to “1'” or “0”, depending on the interrupt configuration specified in the EIT bit. When an interrupt is
triggered, EIF in the EDGEINT Internal Register is set. Reading from EDGEINT will clear the EIF bit.
Internal Register Definition 7. IOCONFIG: Port I/O Configuration
Internal Register Address:
0x00
Reset Value:
0x00
Bit 7-6:
PCIO3.1-PCIO3.0: Port Configuration for GPIO Pin 3
Bit 5-4:
PCIO2.1-PCIO2.0: Port Configuration for GPIO Pin 2
Bit 3-2:
PCIO1.1-PCIO1.0: Port Configuration for GPIO Pin 1
Bit 1-0:
PCIO0.1-PCIO0.0: Port Configuration for GPIO Pin 0
These bits select the port state for GPIO pins 3 through 0.
R/W
PCIO3.1
PCIO3.0
PCIO2.1
PCIO2.0
PCIO1.1
PCIO1.0
PCIO0.1
PCIO0.0
Bit 7
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
Bit 0
PCIOx.1
PCIOx.0
GPIO Pin x Mode
0
Open Drain Output
0
1
Input Only
1
0
Push-Pull Output
1
Input Only
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