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| 型號： | COP8CCR9LVA8 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 43/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU EEPROM 8BIT 68-PLCC |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 59 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 包裝： | 管件 |
| 其它名稱： | *COP8CCR9LVA8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Table 5-7. PGMTIM Register Format (continued)
PGMTIM
Register Bit
CKI Frequency Range
7
6
5
4
3
2
1
0
0
1
0
1
2 MHz–2.67 MHz
0
1
0
1
0
1
0
2.625 MHz–3.5 MHz
0
1
0
1
0
1
3.5 MHz–4.67 MHz
0
1
0
1
4.5 MHz–6 MHz
0
1
0
1
6 MHz–8 MHz
0
1
0
1
7.5 MHz–10 MHz
R
R/W
5.10.4 MANEUVERING BACK AND FORTH BETWEEN FLASH MEMORY AND BOOT ROM
When using ISP, at some point, it will be necessary to maneuver between the flash program memory and
the Boot ROM, even when using customized ISP routines. This is because it's not possible to execute
from the flash program memory while it's being programmed.
Two instructions are available to perform the jumping back and forth: Jump to Boot (JSRB) and Return to
Flash (RETF). The JSRB instruction is used to jump from flash memory to Boot ROM, and the RETF is
used to return from the Boot ROM back to the flash program memory. See Instruction Set for specific
details on the operation of these instructions.
The JSRB instruction must be used in conjunction with the Key register. This is to prevent jumping to the
Boot ROM in the event of run-away software. For the JSRB instruction to actually jump to the Boot ROM,
the Key bit must be set. This is done by writing the value shown in Table 5-8 to the Key register. The Key
is a 6 bit key and if the key matches, the KEY bit will be set for 8 instruction cycles. The JSRB instruction
must be executed while the KEY bit is set. If the KEY does not match, then the KEY bit will not be set and
the JSRB will jump to the specified location in the flash memory. In emulation mode, if a breakpoint is
encountered while the KEY is set, the counter that counts the instruction cycles will be frozen until the
breakpoint condition is cleared. If an interrupt occurs while the key is set, the key will expire before
interrupt service is complete. It is recommended that the software globally disable interrupts before setting
the key. The Key register is a memory mapped register. Its format when writing is shown in Table 5-8. In
normal operation, it is not necessary to test the KEY bit before using the JSRB instruction. The additional
instructions required to test the key may cause the key to time-out before the JSRB can be executed.
Table 5-8. KEY Register Write Format
KEY When Writing
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
X
Bits 7–2:
Key value that must be written to set the KEY bit.
Bits 1–0:
Don't care.
5.10.5 FORCED EXECUTION FROM BOOT ROM
When the user is developing a customized ISP routine, code lockups due to software errors may be
encountered. The normal, and preferred, method to recover from these conditions is to reprogram the
device with the corrected code by either an external parallel programmer or the emulation tools. As a last
resort, when this equipment is not available, there is a hardware method to get out of these lockups and
force execution from the Boot ROM MICROWIRE/PLUS routine. The customer will then be able to erase
the Flash Memory code and start over.
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
37
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