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參數(shù)資料
| 型號： | CM42-67025L-25 |
| 廠商： | ATMEL CORP |
| 元件分類： | SRAM |
| 英文描述： | 8K X 16 DUAL-PORT SRAM, 25 ns, CQCC84 |
| 封裝： | LCC-84 |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 257K |
| 代理商： | CM42-67025L-25 |
M 67025
MATRA MHS
Rev. D (29/09/95)
16
Timing Waveform of Write Cycle n
° 1, R/W Controlled Timing (1, 2, 3, 7)
Timing Waveform of Write Cycle n
° 2, CS Controlled Timing (1, 2, 3, 5)
Notes :
1. R/W must be high during all address transitions.
2. A write occurs during the overlap (tSW or tWP) of a low CS or SEM and a low R/W.
3. tWR is measured from the earlier of CS or R/W (or SEM or R/W) going high to the end of write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high imped-
ance state.
6. Transition is measured
± 500 mV from steady state with a 5pF load (including scope and jig).This parameter is sampled and not
100 % tested.
7. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O
drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during an R/W controlled write cycle, this
requirement does not apply and the write pulse can be as short as the specified tWP.
8. To access RAM, CS = VIL. SEM = VIH.
9. To access upper byte CS = VIL, UB = VIL, SEM = VIH.
To access lower byte CS = VIL, LB = VIL, SEM = VIH.
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