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參數(shù)資料
| 型號： | CLC014AJE-TR13/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 21/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CABLE EQUALIZER ADAPT 14-SOIC |
| 標準包裝： | 2,500 |
| 應(yīng)用： | 醫(yī)用型 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOICN |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
| 配用： | SD901EVK-ND - BOARD EVAL CLC014, 016, 011, 006 SD014EVK-ND - BOARD EVALUATION CLC014 |
| 其它名稱： | *CLC014AJE-TR13 *CLC014AJE-TR13/NOPB CLC014AJE-TR13 |
OBSOLETE
SNLS010E – JUNE 1998 – REVISED APRIL 2013
PIN DEFINITIONS
Name
Pin #
Description
DI, DI
8, 9
Differential data inputs.
DO, DO
13, 14
Differential collector data outputs (ECL compatible).
AEC+, AEC
6, 7
AEC loop filter pins.
A capacitor connected between these pins governs the loop response for the adaptive
equalization loop.
OEM
3
Eye monitor output. The output of the equalization filter.
CD
5
Carrier detect. (Low when no signal is present).
MUTE
12
Output MUTE. (Active low.)
Carrier detect may be tied to this pin to inhibit the output when no signal is present.
VCC
1, 2, 4
Positive supply pins (ground or +5V).
VEE
10, 11
Negative supply pins (
5.2V or ground).
OPERATION
The CLC014 Adaptive Cable Equalizer provides a complete solution for equalizing high-bit-rate digital data
transmitted over long transmission lines. The following sections furnish design and application information to
assist in completing a successful design:
Block diagram explanation of the CLC014
Recommended standard input and output interface connections
Common applications for the CLC014
Measurement, PC layout, and cable emulation boxes
Figure 17. CLC014 Equalizer Application Circuit
Copyright 1998–2013, Texas Instruments Incorporated
9
Product Folder Links: CLC014
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