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參數(shù)資料
| 型號： | CLA71000DP24 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大小： | 243K |
| 代理商： | CLA71000DP24 |
SRB8
SRB8A
SRC8
SRD4
SRE4
2 bit PISO shift register with clear
2 bit PISO shift register without clear
8 bit PISO shift register with clear
8 bit SIPO shift register with clear
4 bit PIPO shift register with JKbar
input
8 bit shift and store register with
tristate outputs
4 bit bidirectional universal shift
register
4 bit parallel access shift register
5 bit shift register
SRF8
SRG4
SRJ4
SRK5
PROCESS MONITOR
PERF
Performance monitor
BIST *
RGBIT
RGTBIT
RGDIAG
RGCTL
RGHOLD
Test register (one bit)
Test register (one monitor bit)
Diagnostic control unit
Test register controller
Test register hold circuitry
* (early built in self test cells) see CLA7BIST Library
CLA70000 PARACELL LIBRARY
MEMORY CELLS
RBRAM
RAM
MAX 16384 bits per block
WORDS 2:128, bits 1:128 (min:max)
ROM MAX 65536 bits per block
WORDS 2:2048, bits 2:64 (min:max)
ROROM
DRL7
BCD to 7 segment decoder/driver
ENCODERS
ENA8T3
ENB10T4
8 line to 3 line priority encoder
10 line to 4 line priority encode
FLIP-FLOP
FFA8
FFB6
FFC4
8 bit bistable latches
6 bit D-type flip-flop with clear
4 bit D-type flip-flop with clear &
complimentary outputs
Octal D-type flip-flop with clear
FFD8
ALU/FUNCTIONAL GENERATOR
FGA5
4 bit ALU/function generator
ADDERS
MCA4
4 bit magnitude comparators
MULTIPLIERS
MLA10
Decade rate multiplier
MLB4X4
4 by 4 binary multiplier with tristate
outputs
MLW7
7 bit Wallace trees with tristate
outputs
MULTIPLEXERS
MXA8T1
8 line to 1 line data selector /
multiplexer
Dual 4 line to 1 line data selector /
multiplexers
Dual 4 line to 1 line data selector /
multiplexer with inverted tristate
outputs
Quad 2 to 1 data selector / multiplexers
Quad 2 to 1 selector (inverted outputs)
4 to 1 multiplexor with strobe
4 to 1 multiplexor with strobe
2 to 1 multiplexeor with storage
MXB4T1
MXB4T1A
MXC2T1
MXC2T1A
MXD4T1
MXE4T1
MXF2T1
PARITY GENERATOR
PGA9
9 bit odd/even parity
generator/checker
SHIFT REGISTERS
SRA2
SRA4
SRA8
SRA8A
SRB2
SRB4
2 bit POS shift register with clear
4 bit POS shift register with clear
8 bit SIPO shift register with clear
8 bit SIPO shift register without clear
2 bit PISO shift register with clear
4 bit PISO shift register with clear
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLA71000DP28 | ASIC |
| CLA71000DP40 | ASIC |
| CLA71000DP48 | ASIC |
| CLA71000GG44 | ASIC |
| CLA71000GG52 | ASIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLA71000DP28 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA71000DP40 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA71000DP48 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA71000GG44 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA71000GG52 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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