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參數(shù)資料
| 型號： | CLA70000MC24 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 243K |
| 代理商： | CLA70000MC24 |
140
90
40
-10
-60
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Normalised Delay Multiplier Vs
temperature
D
Temperature °C
Normalised Delay Multiplier Vs
Voltage
4
4.5
3.5
5
5.5
3
0.8
1
1.2
1.4
1.6
D
(
5
Voltage
AC CHARACTERISTICS FOR SELECTED CELLS
The CLA70000 technology library contains all the timing
information for each cell in the design library. This information
is accessible to the simulator, which calculates propagation
delays for all signal paths in the circuit design. The simulator
can automatically derate timings according to the various
factors such as:
Supply voltage variation (from nominal 5V)
Junction temperature
Processing tolerance - manufacturing spreads
Gate fanout - logic loading on gate outputs
Interconnection wiring - net loading on gate outputs
Fig 6.
Fig 7.
For initial assessments of feasibility, path delay multipliers
can be estimated by referring to the following graphs in
conjunction with the appropriate delays in the tables.
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相關(guān)代理商/技術(shù)參數(shù) |
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| CLA70000MC28 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000MP16L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000MP20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000MP24 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000MP28 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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