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參數(shù)資料
| 型號： | CLA70000MC16 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 243K |
| 代理商： | CLA70000MC16 |
VSS
Supply
VSS
Supply
Programmable
contacts
Fig 1. Diagrammatic representation of Array Core Cell
CORE CELL ARRANGEMENT
I
Supports compact macros
I
Allows high density routing
A four transistor group (2 NMOS and 2 PMOS) (fig.1) forms
the basic cell of the core array. This array element is repeated
in a regular fashion over the complete core area to give an
homogenous ‘Full Field’ (sea of gates) array. This lends itself
to hierarchical design, allowing pre-routed user defined
subcircuits to be repeated anywhere on the array. The core
cell structure together with all associated cell libraries have
been carefully designed to maximize the number of nets
which may be routed through the cell. This enables optimal
routing of both data flow and control signal distribution
schemes thus giving very high overall utilization factors. This
feature is of particular benefit in designs using highly
structured blocks such as memory or arithmetic functions.
I/O BUFFER ARRANGEMENT
I
Several hundred different I/O cell combinations
I
Programmable Slew rate Control on all Outputs
I
Excellent Latchup and ESD immunity
The I/O buffers are the interface to external circuitry and
are therefore required to be robust and flexible. Both inputs
and outputs incorporate electrostatic discharge (ESD)
protection structures which can withstand in excess of 2KV,
and are highly resistant to latch-up due to the epitaxial
process. In addition the construction concepts used for the
I/O cells provide the designer with several hundred different
options of I/O cell configuration.
The CLA70000 I/O buffers (fig.2) contain all the
components for static protection, CMOS and TTL compatible
input stages, and a wide variety of intermediate and output
drive configurations. Included are Schmitt triggers, tristate
controls, and slew rate controlled output buffers. All I/O buffer
locations can be configured as supply pads (VDD and VSS).
Slew rate control of output drivers is a useful feature when
multiple high drive outputs need to be switched
simultaneously, as may occur on driving capacitive loads
such as buses. Using regular output buffers with their
inherently fast edge speed can lead to significant power
supply noise transients, with possible mis-operation as a
result. To overcome this problem. The CLA70000 family
includes a set of slew rate controlled output drivers, which use
proprietary design techniques to control the turn-on of the
output transistors (di/dt). These cells provide a significant
benefit in the trade off between switching current magnitude
and the number of supply pads required.
Fig 2. Slew Control & I/O Block
IP
OP1
OP2
IB1 IB2
Bonding
Pad
PIN
OPT3
N
P
P
N
D
INPUT
DATA
2.5 Volts
2.5 Volts
50 pF
IBSK1, IBSK2 and IBSK3 have been characterised
to give the correct timing when connected to the OPT* cells.
slew rate
controlled
driver
I/O BLOCK
I/O BLOCK
SLEW RATE CONTROL
IB3 IB4 IB5
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| CLA70000MC20 | ASIC |
| CLA70000MC24 | ASIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLA70000MC20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000MC24 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000MC28 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000MP16L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000MP20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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