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參數(shù)資料
| 型號： | CLA70000DP28 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 243K |
| 代理商： | CLA70000DP28 |
MUXI4TO1
MUXI8TO 1
4 to 1 inverting multiplexer
8 to 1 inverting multiplexer
CLKA
2CLKA
CLKAP
CLKAM
CLKB
CLKBP
CLKE1
CLKE2
CLKE3
Basic clock driver
Dual basic clock driver
Basic clock driver + inverter
Basic clock driver + inverter
Large clock driver + inverter
Large clock driver + inverter
Clock driver with enable
Clock driver with enable
Clock driver with enable
TM
2TM
BDR
Buffered transmission gate
Transmission gate for 2 to 1 multiplexing
Internal bus driver
DL
DL2
DLRS
DLARS
DF
DFRS
MDF
MDFRS
Data latch
Data latch
Data latch with set and reset
Data latch with set and reset
Master-slave D type flip flop
Master-slave D type flip flop with set & reset
Multiplexed master-slave D type flip flop
Multiplexed master-slave D type flip flop
with set & reset
Multiplexed m/s D type flip flop
Multiplexed m/s D type flip flop
with set & reset
M3DF
M3DF
JK
JKRS
JBARK
JBARKRS
J-K flip-flop
J-K flip-flop with set & reset
JBAR-K flip-flop
JBAR-K flip-flop with set & reset
BDL
BDLRS
JBARKRS
BDF
BDFRS
Buffered data latch
Buffered data latch with set & reset
Buffered data latch with set & reset
Buffered master-slave D type flip-flop
Buffered master-slave D type flip-flop
with set & reset
Buffered mux. master-slave D type flip-flop
Buffered mux. m/s D type with set & reset
Buffered J-K flip-flop
Buffered J-K flip-flop with set & reset
BMDF
BMDFRS
BJBARK
BJBARKRS
TRID
Tristate driver
GND
VDD
Ground Cell
VDD Cell
INTERMEDIATE BUFFER CELLS
IBCCMOS1
IBCCMOS2
IBTTL1
IBBTL2
IBST1
CMOS input buffer + large 2 input NAND gate
CMOS input buffer + data latch
TTL input buffer + large 2 input NAND gate
TTL input buffer + data latch
Input Schmitt buffer with CMOS switching
levels
Input Schmitt buffer with 2V switching levels
IBST2
IBGATE
IBCLKB
IBDF
IBDFA
IBSK1
IBSK2
IBSK3
IBTRID
IBTRID1
NAND2/NOR2 gates
Large clock driver
Master-slave D type flip flop
Master-slave D type flip flop
Driver with slewed outputs
Driver with slewed outputs
Driver with slewed outputs
Tri-state driver
Tri-state driver with slewed outputs +
2 inverters
Tri-state driver with slewed outputs +
2 inverters
Tri-state driver with slewed outputs +
2 inverters
Dual high powered inverters
IBTRID2
IBTRID3
IB2BD
DRV3
DRV6
Clock driver
Clock driver
PAD INPUT CELLS
IPNR
IPR1P
IPR1M
IPR2P
IPR2M
IPR3P
IPR3M
IPR4P
IPR4M
Input cell with no pull up or down resistors
Input cell with 1KOhm pull up resistor
Input cell with 1KOhm pull down resistor
Input cell with 2KOhm pull up resistor
Input cell with 2KOhm pull down resistor
Input cell with 4KOhm pull up resistor
Input cell with 4KOhm pull down resistor
Input cell with 75KOhm pull up resistor
Input cell with 75kOhm pull down resistor
OSCILLATOR CELLS
(crystal)
to be defined
PAD OUTPUT CELLS
OP1
OP2
OP3
OP6
OP12
Smallest drive output cell
Small drive output cell
Standard drive output cell
Medium drive output cell
Large drive output cell
OP5B
OP11B
Standard drive non-inverting output cell
Large drive non-inverting output cell
OPT1
OPT2
OPT3
OPT6
OPT12
Smallest drive tri-state output cell
Small drive tri-state output cell
Standard drive tri-state output cell
Medium drive tri-state output cell
Large drive tri-state output cell
OP4B
Standard drive non-inverting tri-state output
cell
Large drive non-inverting tri-state output cell
OP10B
OPOD1
OPOD2
OPOD3
OPOD6
OPOD12
Smallest drive open-drain output cell
Small drive open-drain output cell
Standard drive open-drain output cell
Medium drive open-drain output cell
Large drive open-drain output cell
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLA70000DP40 | ASIC |
| CLA70000DP48 | ASIC |
| CLA70000GG44 | ASIC |
| CLA70000GP44 | ASIC |
| CLA70000HC28 | ASIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLA70000DP40 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000DP48 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000GG44 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000GP44 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000HC28 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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