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參數(shù)資料
| 型號(hào)： | CLA70000DC40 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁(yè)數(shù)： | 11/17頁(yè) |
| 文件大小： | 243K |
| 代理商： | CLA70000DC40 |
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PDS2 - THE GPS ASIC DESIGN SYSTEM
I
Behavioral, Functional, and Gate Level Modelling
I
VHDL and Third Party Links
I
Supports Hierarchical Design Techniques
I
EDIF 2.0 Interface
PDS2 is GPS’s own proprietary ASIC design system. It
provides a fully-integrated, technology independent VLSI
design environment for all GPS CMOS SemiCustom
products.
PDS2 runs on Digital Equipment Computers and is self
configuring according to the available machine resources. It
comprises design capture (schematic capture or VHDL),
testability analysis, logic simulation, fault simulation, auto
place and route, and back annotation. The system offers full
support for hierarchical design techniques, maintained from
design capture through to layout, as well as advanced design
management tools. PDS2 may be used either at a GPS
Design Center or under licence at the customer’s premises. A
three day training course is available for first time users.
THIRD PARTY SOFTWARE SUPPORT
I
Design Kits for major industry standard ASIC design
software tools
I
All libraries include fully detailed timing information
I
EDIF 2.0 Interface
I
Post layout back annotation available
GPS supports a wide range of third party design tools
including IKOS, Mentor, Verilog, and Viewlogic at the time of
printing. Please check with our Sales Offices for the most
recent additions. The design kits offer fully detailed timing
information for all cell libraries, netlist extraction utilities, and
post layout back annotation capability where applicable. An
example of a workstation design flow is shown in fig 5 below.
Please contact your local GEC Plessey Semiconductor’s
sales office for further information about support of particular
tools.
Fig 5. Workstation Design Flow
SPECIFICATIONS
THERMAL MANAGEMENT
I
Lower power CMOS for better thermal management
I
Improved reliability
I
Power packages available
The increase in speed and density available through
CMOS process geometry reduction, results in a
corresponding increase in power dissipation. SemiCustom
designers now have the ability to design circuits of 100,000
gates and over, and chip power consumption is (or should be)
a very important concern.
The logic core of 100K plus gates is the dominant factor
in power dissipation at this complexity. It is essential to offer
ultra low power core logic to maintain an acceptable overall
chip power budget.
To minimize this problem GPS’s CLA70000 arrays offer
low power factors and a selection of power packages.
Dissipation of 5
μ
W per gate per Mhz gate power and 1
μ
W per
gate load, is lower than most competitive arrays, with the
reduced junction temperatures having the added advantage
of improved performance and reliability.
CLA70000 POWER DISSIPATION CALCULATION
CLA70000 series power dissipation for any array can be
estimated by following the example (calculated for the CLA76XXX)
below.
Number of available gates
Assume percent gates used
Number of used gates (110102 X 0.4)
Assume 15% of gates switching during.
each clock cycle (44045 X 0.15)
Power dissipation/gate/Mhz
(gate fanout typically 2 loads)
110112
40%
44045
6607
7
μ
W
Total core dissipation/Mhz (6607 X 0.007)
46.2 mW
Number of available I/O pads
200
Percent of I/O pads used as Outputs
Number of I/O pads used as Outputs
Number of output buffers switching
each clock cycle (20%)
40%
80
16
Dissipation/output buffers/Mhz/pF
Output loading
25
μ
W
50 pF
Power/output buffer/Mhz
Total output buffer dissipation/Mhz
1.25mW
20mW
Total Power dissipation/Mhz
66.2mW
Estimated dissipation of the circuit at the frequencies below is
Total Power at 10 Mhz clock rate
Total Power at 25Mhz clock rate
0.66W
1.65W
Schematic
Capture
Test Vector
Generation
Simulation
Vector
Translation
Back -
Annotation
ERC &
Netlist
Translation
Schematic
Symbols
CLA
Libraries
Simulation
Models
MLE
Place &
Route
Design
Verification
Test Program
Generation
PDS
WORKSTATION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLA70000DC48 | ASIC |
| CLA70000DP16 | ASIC |
| CLA70000DP22 | ASIC |
| CLA70000DP24 | ASIC |
| CLA70000DP28 | ASIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLA70000DC48 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000DP16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000DP22 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000DP24 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA70000DP28 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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