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| 型號： | CL7256AETI144-7 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 176K |
| 代理商： | CL7256AETI144-7 |
CL7256A and CL7256AE Laser Processed Logic Devices
Page 13
1. During transitions, inputs may undershoot to -2.0V for periods shorter than
20ns. Otherwise, minimum DC input voltage is 0.3V.
2. Typical values are at V
CC
of 5.0 volts and ambient temperature of 25 oC.
3. Guaranteed but not tested. Characterized initially, and after any design
changes which may affect these parameters.
4. Internal timing delays are based on characterization, and cannot be explicitly
tested. Internal timing parameters should be used for performance estimation
only.
11 Jan. 1999:
31 July 1999:
13 Oct. 1999:
Created preliminary document.
Created full document.
Corrected typographical error in AC Test Condition diagram (W
changed to
W
) also corrected timing in 10ns External Timing
Paramiters
Updated application note reference.
1 Dec. 2000:
AC Test Conditions
464
250
35 pF
V
CCIO
OUTPUT
Includes jig
capacitance
464
250
5 pF
V
CCIO
OUTPUT
Includes jig
capacitance
(A)
(B)
≤
3ns
≤
3ns
3.0V
90%
10%
GND
90%
10%
All Input Pulses
7K drw 02A
Notes to Tables
Revision History
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