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| 型號： | CK-V6-ML623-G |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DEV V6 WITH TX |
| 產(chǎn)品培訓(xùn)模塊： | Virtex-6 FPGA Overview |
| 標準包裝： | 1 |
| 系列： | Virtex® 6 LXT |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | Virtex? 6 LXT，XC6VLX240T |
| 所含物品： | 板，線纜，文檔，電源 |
Virtex-6 Family Overview
DS150 (v2.4) January 19, 2012
Product Specification
7
Input/Output
The number of I/O pins varies from 240 to 1200 depending on device and package size. Each I/O pin is configurable and can
comply with a large number of standards, using up to 2.5V. The Virtex-6 FPGA SelectIO Resources User Guide describes
the I/O compatibilities of the various I/O options. With the exception of supply pins and a few dedicated configuration pins,
all other package pins have the same I/O capabilities, constrained only by certain banking rules.
All I/O pins are organized in banks, with 40 pins per bank. Each bank has one common VCCO output supply-voltage pin,
which also powers certain input buffers. Some single-ended input buffers require an externally applied reference voltage
(VREF). There are two VREF pins per bank (except configuration bank 0). A single bank can have only one VREF voltage
value.
I/O Electrical Characteristics
Single-ended outputs use a conventional CMOS push/pull output structure driving High towards VCCO or Low towards
ground, and can be put into high-Z state. The system designer can specify the slew rate and the output strength. The input
is always active but is usually ignored while the output is active. Each pin can optionally have a weak pull-up or a weak pull-
down resistor.
Any signal pin pair can be configured as differential input pair or output pair. Differential input pin pairs can optionally be
terminated with a 100
Ωinternal resistor. All Virtex-6 devices support differential standards beyond LVDS: HT, RSDS, BLVDS,
differential SSTL, and differential HSTL.
Digitally Controlled Impedance
Digitally controlled impedance (DCI) can control the output drive impedance (series termination) or can provide parallel
termination of input signals to VCCO, or split (Thevenin) termination to VCCO/2. DCI uses two pins per bank as reference pins,
but one such pair can also control multiple banks. VRN must be resistively pulled to VCCO, while VRP must be resistively
connected to ground. The resistor must be either 1× or 2× the characteristic trace impedance, typically close to 50
Ω.
I/O Logic
Input and Output Delay
This section describes the available logic resources connected to the I/O interfaces. All inputs and outputs can be configured
as either combinatorial or registered. Double data rate (DDR) is supported by all inputs and outputs. Any input or output can
be individually delayed by up to 32 increments of ~78 ps each. This is implemented as IODELAY. The number of delay steps
can be set by configuration and can also be incremented or decremented while in use.
For using either IODELAY, the system designer must instantiate the IODELAY control block and clock it with a frequency
close to 200 MHz. Each 32-tap total IODELAY is controlled by that frequency, thus unaffected by temperature, supply
voltage, and processing variations.
ISERDES and OSERDES
Many applications combine high-speed bit-serial I/O with slower parallel operation inside the device. This requires a
serializer and deserializer (SerDes) inside the I/O structure. Each input has access to its own deserializer (serial-to-parallel
converter) with programmable parallel width of 2, 3, 4, 5, 6, 7, 8, or 10 bits. Each output has access to its own serializer
(parallel-to-serial converter) with programmable parallel width of up to 8 bits wide for single data rate (SDR), or up to 10 bits
wide for double data rate (DDR).
System Monitor
Every Virtex-6 FPGA contains a System Monitor circuit providing thermal and power supply status information. Sensor
outputs are digitized by a 10-bit 200kSPS analog-to-digital converter (ADC). This fully tested and specified ADC can also be
used to digitize up to 17 external analog input channels. The System Monitor ADC utilizes an on-chip reference circuit
thereby eliminating the need for any external active components. On-chip temperature and power supplies are monitored
with a measurement accuracy of ±4°C and ±1% respectively.
By default the System Monitor continuously digitizes the output of all on-chip sensors. The most recent measurement results
together with maximum and minimum readings are stored in dedicated registers for access at any time through the DRP or
JTAG interfaces. User defined alarm thresholds can automatically indicate over temperature events and unacceptable power
supply variation. A specified limit (for example: 125°C) can be used to initiate an automatic power down.
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| CK-V6-ML623-G-J | 功能描述:BOARD DEV V6 WITH TX RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex® 6 LXT 標準包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
| CK-V6-ML628-G | 功能描述:KIT VIRTEX-6 CHAR ML628 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex® 6 標準包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
| CK-V6-ML628-G-J | 功能描述:KIT VIRTEX-6 CHAR ML628 JAPAN RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex® 6 標準包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
| CK-V7-VC7203-G | 制造商:Xilinx 功能描述:VIRTEX-7 FPGA VC7203 CHARACTERIZATION KIT - Boxed Product (Development Kits) 制造商:Xilinx 功能描述:KINTEX-7 FPGA VC7203 EVAL KIT |
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